Intel IXP1200 manual Global Counter Enable and Flags, Counter Flags, #define Statement Description

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

4.8.2.3Global Counter Enable and Flags

Global Counter Enable and Flags

COUNTERS_ENABLE_MASK is the global counter enable and is set via a #define statement in system_config.h:

#define Statement	Description

COUNTERS_ENABLE_MASK 0xFFFFFFFF	Enable all counters (default).

COUNTERS_ENABLE_MASK 0	Disable all counters.

To enable a counter for a command:

1.Ensure that the COUNTERS_ENABLE_MASK is set to enable.

2.Set the individual command’s IN_ENABLE_FLAGS parameter to match the COUNTERS_ENABLE_MASK definition.

Counter Flags

The counters are enabled by membership in the “counter groups” enumerated in the table; the counter groups are enabled by having their corresponding bit set in the

COUNTERS_ENABLE_MASK.

The default COUNTERS_ENABLE_MASK enables all the error counters and disables all the normal counters in an effort to record abnormal events without a measurable performance impact.

For example, the following definition enables just the cell and packet drop related counters.

#define COUNTERS_ENABLE_MASK (COUNT_CELL_DROP COUNT_PACKET_DROP)

For the benefit of counters_print(), system_config.h also defines a string for each counter. For example:

#define COUNTER_STRING2 "ATM_RX_CELL_DROP_VC_CLOSED"

While this could be any string, in the interest of brevity, generally just the name of the associated counter handle is used.

The counters are partitioned into 10 groups - each group with a unique flag:

Counter	Group	Description

COUNT_CELL	(1 << 1)	normal per-cell activity

COUNT_CELL_DROP	(1 << 2)	dropped cells

COUNT_PACKET	(1 << 3)	normal per-packet activity

COUNT_PACKET_DROP	(1 << 4)	dropped packets

COUNT_BUFFER	(1 << 5)	normal buffer (push/pop) activity

COUNT_BUFFER_FAIL	(1 << 6)	buffer subsystem failures

COUNT_QUEUE	(1 << 7)	normal enqueue/dequeue events

48	Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowMicroengine Functional Blocks Microengine InitializationATM Receive Microengine StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorSoftware Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryEntry Description Buffer Offset Buffer IndexCell data11 Entry Description VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureIP Lookup Table VC Cache APIIP Table Function IP Table StructureIP Table Management API RoutetableinitMtuchange AtmrouteaddEnetrouteadd RtentinfoRoutedelete RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdrSequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call DescriptionMessage Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line AnalogyMsgqhandle Parameters MsgqinitqueueMsgqinitregs MsgqsendMsgqreceive Ramoption1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management MacrosCounters CountGlobal Parameters Use of the Counter SubsystemCounter Base Address Counter IndexGlobal Counter Enable and Flags Counter Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutex Vectors MutexvectorinitMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description