Intel IXP1200 manual IP Table Management API, Routetableinit, Mtuchange, Atmrouteadd

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

4.3.3IP Table Management API

The route table is managed by the Route Table Manager (RTM), which may be used from both Transactor Scripts and VxWorks. It may be compiled and loaded as a local foreign model, thus allowing its C functions to be called from a Transactor Script. Or, it can be compiled as a VxWorks loadable object.

The API may be printed out by entering rt_help() at the command line of either VxWorks, or the Transactor simulator.

4.3.3.1route_table_init()

Initializes route table memory and data structures.

route_table_init(int sram_base_addr, int dram_base_addr)

Parameter

Description

 

 

sram_base_addr

The starting address of the SRAM memory allocated for route lookup entries.

 

 

dram_base_addr

The starting address of the DRAM memory allocated for the route table entries.

 

 

4.3.3.2mtu_change()

Sets the MTU for subsequent route table additions.

mtu_change(int new_mtu)

Parameter

Description

 

 

int new_mtu

New default MTU.

 

 

4.3.3.3atm_route_add()

Adds a route for ATM destination to the route table.

atm_route_add(char *dest, char *netmask,char *gateway, int port_type,int queue_index,int atm_hdr,int llc_snap_hi, int llc_snap_lo)

Parameter

Description

 

 

char *dest

String IP destination, e.g. "1.1.1.1"

 

 

char *netmask

String netmask, e.g., "255.255.0.0"

 

 

char *gateway

String next hop gateway, e.g., "255.255.0.0"

 

 

int port_type

Type of port.

 

 

int queue_index

Index of the output queue.

 

 

int atm_hdr

vpi/vci for the connection.

 

 

int llc_snap_hi

hi 32 bits of llc/snap header.

 

 

int llc_snap_lo

lo 32 bits of llc/snap header.

 

 

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Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowMicroengine Functional Blocks Microengine InitializationATM Receive Microengine StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorSoftware Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryEntry Description Buffer Offset Buffer IndexCell data11 Entry Description VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureIP Lookup Table VC Cache APIIP Table Function IP Table StructureIP Table Management API RoutetableinitMtuchange AtmrouteaddEnetrouteadd RtentinfoRoutedelete RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdrSequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call DescriptionMessage Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line AnalogyMsgqhandle Parameters MsgqinitqueueMsgqinitregs MsgqsendMsgqreceive Ramoption1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management MacrosCounters CountGlobal Parameters Use of the Counter SubsystemCounter Base Address Counter IndexGlobal Counter Enable and Flags Counter Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutex Vectors MutexvectorinitMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description