Intel IXP1200 manual ATM Transmit Microengine, ATM Transmit High Level Algorithm

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

3.2ATM Transmit Microengine

The ATM Transmit microengine is an AAL5 Unspecified Bit Rate (UBR) Transmitter that uses a single microengine to move cells at wire-rate in either single OC-12 or up to four OC-3 port configurations. No attempt is made to mix, schedule, or otherwise ’shape’the order of the cells on the wire.

The transmitter consumes PDUs one at a time from beginning to end, resulting in an output stream in which cells from the same PDU are transmitted "back-to-back" from first through the last cell of the PDU.

The transmitter is implemented with 3 identical fill threads. Unlike the Ethernet transmitter, the ATM transmitter does not have a thread dedicated to scheduling the work of the fill threads. Rather, the fill threads use shared absolute registers to act as a "distributed scheduler". The fourth thread could also be enabled as a fill thread, but is not needed at the wire rates in this design.

In IXP1240/1250 hardware CRC configurations, the ATM Transmitter generates CRC-32 upon transferring cells from DRAM to the TFIFO. In the IXP1200 software CRC configurations, CRC-

32 is computed by a dedicated CRC-32 generation microengine.

3.2.1High Level Algorithm

Figure 13. ATM Transmit High Level Algorithm

while(1) critsect_enter(@poll_for_new_work_mutex) if (engine not active sending a PDU)

dequeue a PDU

if (Rosetta not ready to transmit) goto skip#

critsect_exit(@poll_for_new_work_mutex)

get transmit (cell) assignment from active PDU

sequence_enter(SEQ_TFIFO) - remember TIFO element allocation order _atm_tfifo_element() to claim the next TIFO element

write payload from DRAM to TFIFO

_build_atm_tx_assignment() set-up TFIFO control word _my_tfifo_status_write() write control to TFIFO atm_tx_tfifo_write_cell_header_and_data0() – ATM header into TFIFO sequence_wait(SEQ_TFIFO) - wait for my element to be next

tfifo_ptr_wait() - don't validate too far ahead of xmit_ptr tfifo_validate_write()

sequence_exit(SEQ_TFIFO) continue

skip#: // skip a TIFO element critsect_exit(@poll_for_new_work_mutex) sequence_enter(SEQ_TFIFO) - remember TIFO element allocation order _atm_tfifo_element() - to claim the next TIFO element _my_tfifo_skipstatus_write() - write control to TFIFO sequence_wait(SEQ_TFIFO) - wait for my element to be next

tfifo_ptr_wait() - don't validate too far ahead of xmit_ptr tfifo_validate_write()

sequence_exit(SEQ_TFIFO)

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Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowATM Receive Microengine Microengine Functional BlocksMicroengine Initialization StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorCRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache StructureIP Table Function IP Lookup TableVC Cache API IP Table StructureMtuchange IP Table Management APIRoutetableinit AtmrouteaddRoutedelete EnetrouteaddRtentinfo RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Next BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdrSequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call DescriptionExample Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line AnalogyMsgqinitregs Msgqhandle ParametersMsgqinitqueue MsgqsendMsgqreceive RamoptionBuffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management MacrosCounters CountCounter Base Address Global ParametersUse of the Counter Subsystem Counter Index#define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group DescriptionCounterinc Counters.uc CounterresetPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutexvectorenter Mutex VectorsMutexvectorinit MutexvectorexitInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description
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