Intel IXP1200 manual Buffer Descriptor Queues bdq.uc, BDQ Management Macros, Features, Limitations

Page 45

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

... ; process the message, threads may get out of order. move(message, $xfer)

sequence_wait(MY_SEQUENCE) ; wait until it is my turn to send msgq_send(message, $xfer, MY_MSGQ, ctx_swap)

.if (message != 0) counter_inc(OUTPUT_MSGQ_IS_FULL) ; record failure buf_push(message, ...)

;if message is descriptor, return it...

.endif

sequence_exit(MY_SEQUENCE)

;allow next thread through sequence_wait()

4.7Buffer Descriptor Queues - bdq.uc

This design uses a generic buffer descriptor queuing subsystem to pass data between microengines. This section describes the facility so that it will be clear when it is applied throughout the design.

Buffer Descriptor Queues (BDQs) are analogous to packet queues, as defined in packetq.uc and tx.uc. BDQs support cached dequeues, and are therefore more efficient when a microengine dequeues from a small number of queues.

4.7.1BDQ Management Macros

Buffer descriptor queue management macros are used for queueing SRAM buffer descriptors between microengines.

4.7.1.1

Features

 

 

 

 

 

 

 

Feature

Description

 

 

 

 

 

 

 

Queues are implemented via a linked list of buffer descriptors in SRAM.

 

Arbitrary queue capacity

These lists can grow to any size up to a configurable water mark, or the

 

 

 

enqueuing microengine exhausts its supply of available buffers.

 

 

 

 

 

 

 

The queue handle has settings for LWMs and HWMs to manage queue

 

High water marks (HWMs)

length. bdq_enqueue() will reject all enqueues when the queue size is above

 

and low water marks (LWMs)

the HWM. bdq_enqueue() will reject a handle-specified ratio of the enqueues

 

 

 

when queue length is between LWM and HWM.

 

 

 

 

 

Non-blocking simultaneous

If the queue has more than 1 entry, then the dequeuing thread can perform a

 

"cached deqeueue" where it not only doesn’t contend for the lock on the

 

enqueue and dequeue

 

queue header, it doesn’t read the queue header at all

 

 

 

 

 

 

 

 

Empty queue notification

The dequeuing threads have the option of sleeping on an inter-thread signal if

 

the queue is empty.

 

 

 

 

 

 

 

4.7.1.2Limitations

For the dequeue front of queue to be cached by the dequeuing microengine, a single microengine must be assigned to dequeue from each queue, and must have three available absolute registers.

Application Note

45

Modified on: 3/20/02,

Page 44 Page 46
Image 45
Page 44 Page 46
Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationMicroengine Initialization Microengine Functional BlocksATM Receive Microengine StructureOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCVirtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cEntry Description Buffer Offset Buffer IndexCell data11 Entry Description 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureVC Cache API IP Lookup TableIP Table Function IP Table StructureRoutetableinit IP Table Management APIMtuchange AtmrouteaddRtentinfo EnetrouteaddRoutedelete Rthelp2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersSram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdrSystem Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call DescriptionUsage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line AnalogyMsgqinitqueue Msgqhandle ParametersMsgqinitregs MsgqsendRamoption MsgqreceiveFeature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management MacrosCount CountersUse of the Counter Subsystem Global ParametersCounter Base Address Counter IndexCounter Flags Global Counter Enable and Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorinit Mutex VectorsMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... BytesTitle Description Related Documents
Top Page Image Contents