Intel IXP1200 manual IP-Router Microengine, Ethernet Receive Microengine

Page 23

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

3.3IP-Router Microengine

The IP Router microengine consumes packets from the ATM receive microengine via a message queue, and routes them to the appropriate Ethernet transmit packetq. In the IXP1200 software-CRC configuration, this function is carried out by two threads residing on the ATM Receive microengine rather than on a dedicated IP router microengine.

3.3.1Structure

All threads are identical. In hardware-CRC configurations, four IP Router threads reside on the dedicated IP-router microengine. In the software-CRC configuration, two IP Router threads reside on the ATM Receive microengine.

3.3.2High Level Algorithm

Figure 14. IP Router High Level Algorithm

while(1)

msgq_receive() packet from ATM RX engine ip_filter() out SNMP, IGMP

ip_addr_validation() to discard packets from reserved addresses

ip_dbcast_check() to filter out packets from directed broadcast addresses ip_proc()

ip_verify() check TTL and checksum ip_modify() update TTL

ip_route_lookup()

port_enabled_check() to discard packets from disabled port update Ethernet MAC Source Address with our own

#ifdef ATM_LOOPBACK //Allow hardware configurations with ATM outputs //connected directly to ATM inputs

if(output port == ATM port)

over-ride ATM destination port with round-robin Ethernet port

#endif

packetq_send() packet to destination Ethernet port

3.4Ethernet Receive Microengine

The Ethernet Receive microengine is based on rx_ether100m.uc, an extended version of the Ethernet receive threads from the Software Development Kit’s (SDK's) 16-port Ethernet example design1. While the code looks quite different from that on the SDK, most of the changes required a simple move to a more efficient structure, without changing the logical function of the microengine. For example, the threads take advantage of updated APIs for the RFC1812 macros to lower the overhead of RFC1812 support.

Semantically, there are only a few differences from the SDK Ethernet design.

IP lookup can return an ATM destination port, or an Ethernet destination port.

For ATM destinations, prepend the LLC/SNAP to the payload.

For ATM destinations, append the AAL5 trailer.

1.The SDK (Software Development Kit) 2.01 CD contains a number of earlier IXP1200 Ethernet example designs that have remained relatively unchanged from previous releases of the SDK. The Ethernet receive and transmit code in this example design reuses that code with few modifications

Application Note

23

Modified on: 3/20/02,

Image 23
Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionPortcounterinc Counters.uc CounterresetCounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents