Intel IXP1200 manual CRC-32 Hardware Generation on Transmit, Transmit Alignment

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Upon reception of the first cell, data11 is saved in the VC cache/table entry. Upon reception of the 2nd cell, data11 is retrieved from the VC cache/table entry, combined with data0 of the second cell, and written in a single burst to DRAM.

Moving the nth cell (not cell0) in a PDU from the RFIFO to DRAM is similar to using the macro atm_move_cell0_rfifo_to_sdram(), except that:

The nth cell must start with a run-time crc_residue resulting from CRC on the previous cell in the PDU.

The nth cell must combine data11 of the previous cell with data0, as shown in Figure 17.

3.6.2CRC-32 Hardware Generation on Transmit

Figure 18 and Figure 19 show the layout of the cell source as it appears in DRAM, and the desired format in the TIFO, respectively. Aspects of the first, nth, and last cell are all overlaid on the same diagram, as the positions are the same. In each diagram, rows are 64-bit “quadwords”.

Figure 18. Transmit cell as seen in DRAM

 

0

1

2

3

4

5

6

 

7 Bytes -> (Big Endian Diagram)

 

 

 

 

 

 

 

 

 

 

 

0

-

-

-

-

-

-

LLC

 

 

 

 

 

 

 

 

 

 

 

 

 

1

LLC

 

 

 

 

 

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

2

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

AAL5

 

 

 

 

 

 

 

 

 

 

 

 

6

AAL5

 

CRC32*

 

 

CellN+1

 

 

 

 

 

 

 

 

 

 

 

 

Figure 19. Transmit cell seen in TFIFO

 

0 1 2

3 4

 

5

6

7 Bytes -> (Big Endian Diagram)

 

 

 

 

 

 

 

 

 

 

 

0

ATM Header

 

LLC

 

 

 

 

 

 

 

 

 

 

 

 

1

LLC1

 

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

2

IP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

IP

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

AAL5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

CRC32

 

-

 

-

-

-

 

 

 

 

 

 

 

 

 

 

 

 

3.6.2.1Transmit Alignment

The alignment of this cell in DRAM is dependent on how the data was received. In this example design, the data was received on Ethernet, with a 14 byte Ethernet header. Therefore, the first byte of the IP header starts on the 15th byte of the buffer.

The sdram_crc[t_fifo_wr] commands account for this alignment by using the IXP12xx byte alignment hardware. These diagrams show bytes in big-endian order, while the instruction encoding asks for byte alignment assuming little endian order. Therefore the 6-byte offset shown here, becomes a 2-byte offset as encoded in the indirect_ref.

Application Note

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Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cEntry Description Buffer Offset Buffer IndexCell data11 Entry Description VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersSram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionCounters.uc Counterreset CounterincPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents