Intel IXP1200 manual Buffer Offset Buffer Index, Cell data11 Entry Description

Page 33

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Entry

Description

 

 

Next

Address of the next entry in the chain of entries that hash to the same row. 0 indicates no

next entry. (21 bit SRAM address)

 

 

 

Key

Hash key used to find this entry, also used to confirm arrival at the desired entry. Key =

(atm_header & 0xFFFFFFF0) port#

 

 

 

Buffer Offset

Indicates which 64-bit DRAM word in the buffer should receive the next payload. On

completion of PDU assembly, this field is copied to the buffer descriptor.

 

 

 

Buffer Index

Buffer descriptor (and data buffer) to be used by ATM Receive to deposit payloads on this

VC.

 

 

 

LLC/SNAP

1: LLC0_IP, LLC1_IP

else: available for other patterns

 

 

 

 

Queue To StrongARM core "Q" flag

Q

1: queue all traffic to core

 

0: do not queue to core

 

 

AAL

5: ATM Adaptation Layer 5

0: VC is not open

 

 

 

CRC

The CRC-32 syndrome associated with the PDU. It is saved in the VC table entry after a cell

is moved, and then retrieved and used when the next cell in the PDU is received.

 

 

 

 

The last four bytes of the previous cell in this PDU. Used during re-assembly of PDUs to

Cell Data11

allow 8-byte quadword burst writes to DRAM without using DRAM Read/Modify/Write

 

instructions.

 

 

Figure 24. VC Lookup Table Entry (VC_TABLE_LINEAR)

0

1

2

3

3

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

1

1

9

8

7

6

5

4

3

2

1

0

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer Offset

 

 

 

 

 

 

 

 

Buffer Index

 

 

 

 

 

 

LLC/SNAP

Q

 

AAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CRC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cell data11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Entry

Description

 

 

Buffer Offset

Indicates which 64-bit DRAM word in the buffer should receive the next payload. On

completion of PDU assembly, this field is copied to the buffer descriptor.

 

 

 

Buffer Index

Buffer descriptor (and data buffer) to be used by ATM Receive to deposit payloads on this VC.

 

 

LLC/SNAP

1: LLC0_IP, LLC1_IP

else: available for other patterns

 

 

 

 

Queue To StrongARM core "Q" flag

Q

1: queue all traffic to core

 

0: do not queue to core

 

 

Application Note

33

Modified on: 3/20/02,

Page 32 Page 34
Image 33
Page 32 Page 34
Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationMicroengine Initialization Microengine Functional BlocksATM Receive Microengine StructureOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCVirtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cEntry Description Buffer Offset Buffer IndexCell data11 Entry Description 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureVC Cache API IP Lookup TableIP Table Function IP Table StructureRoutetableinit IP Table Management APIMtuchange AtmrouteaddRtentinfo EnetrouteaddRoutedelete Rthelp2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersSram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdrSystem Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call DescriptionUsage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line AnalogyMsgqinitqueue Msgqhandle ParametersMsgqinitregs MsgqsendRamoption MsgqreceiveFeature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management MacrosCount CountersUse of the Counter Subsystem Global ParametersCounter Base Address Counter IndexCounter Flags Global Counter Enable and Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorinit Mutex VectorsMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... BytesTitle Description Related Documents
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