Intel IXP1200 manual Counters.c Countersinit, Countersprint

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

4.8.4counters.c

4.8.4.1counters_init()

Initializes all counters.

4.8.4.2counters_print()

Prints the names and values of all counters.

Example

In this example of output from counters_print(), the system ran the dual-OC-3 software-CRC configuration overnight with an ATM loop-back cable. All counters were enabled. The first column is the word’s location in scratchpad RAM, the second column, the number in [] brackets, is the counter index, the third column is the counter value, and after that starts a string identifying the counter. At the end we see a few of the per-port counters have incremented as well.

-> counters_print
195:[ 0]:	32	ATM_RX_CELL_IDLE
196:[ 1]: 1688083162		ATM_RX_FIRST_CELLS
197:[ 2]: 3376166321		ATM_RX_CELLS_MOVED
198:[ 3]: 1688083167		ATM_RX_LAST_CELLS
199:[ 4]:	0	ATM_RX_CELL_DROP_NOT_USER
200:[ 5]:	0	ATM_RX_CELL_DROP_VC_CLOSED
201:[ 6]:	9	ATM_RX_CELL_DROP_LLC_SNAP
202:[ 7]:	0	ATM_RX_PDU_DROP_AAL5_LENGTH
203:[ 8]:	0	ATM_RX_CELL_DROP_NO_BUFFERS_ON_RX
204:[ 9]:	0	ATM_RX_IP_OPTIONS_OR_FRAG_Q2CORE
205:[10]:	4	ATM_RX_CRC_BAD
206:[11]:	0	ATM_RX_SNMP
207:[12]:	0	ATM_RX_ICMP
208:[13]:	0	ATM_RX_IGMP
209:[14]:	0	ATM_RX_PORT_RXCANCEL
210:[15]:	0	ATM_RX_VC_LOOKUP_ERROR
211:[16]: 3316353954		ETHER_RX_SOPS
212:[17]: 3316353962		ETHER_RX_EOPS
213:[18]:	0	ETHER_RX_MPACKETS_MOVED
214:[19]:	0	ETHER_RX_DROP_NOT_IPV4
215:[20]:	0	ETHER_RX_DROP_MULTICAST
216:[21]:	0	ETHER_RX_DROP_BROADCAST
217:[22]:	0	ETHER_RX_IP_OPTIONS_OR_FRAG_Q2CORE
218:[23]:	0	ETHER_RX_SNMP
219:[24]:	0	ETHER_RX_ICMP
220:[25]:	0	ETHER_RX_IGMP
221:[26]:	0	Counter 26
222:[27]:	0	Counter 27
223:[28]:	0	Counter 28
224:[29]:	0	Counter 29
225:[30]: 1688085155		ATM_RX_ALLOC_BUFFER
226:[31]:	0	ATM_RX_ALLOC_BUFFER_FAIL
227:[32]: 3316355686		ETHER_RX_ALLOC_BUFFER
228:[33]:	0	ETHER_RX_ALLOC_BUFFER_FAIL
229:[34]: 1688087130		ATM_TX_BUF_PUSH
230:[35]: 1688085175		ETHER_TX_BUF_PUSH
231:[36]:	0	BUF_POP_BAD_BDA
232:[37]:	0	BUF_PUSH_BAD_BDA
233:[38]:	0	Counter 38
234:[39]:	0	Counter 39
235:[40]:	0	ATM_RX_PKT_ENQUEUE_ETHER
236:[41]: 1805817709		ETHER_RX_PDU_ENQUEUE_ATM

Application Note

51

Modified on: 3/20/02,

Image 51

Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cEntry Description Buffer Offset Buffer IndexCell data11 Entry Description VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersSram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionCounters.uc Counterreset CounterincPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents