Intel IXP1200 manual Message Queues msgq.uc, Usage Model, Example

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

4.5.2Usage Model

The following model is described by an analogy to waiting in line at a bakery:.

Step

Sequence Operation

Bakery Line Analogy

 

 

 

 

sequence_enter() returns a sequence number to a thread

 

1

and updates the absolute.enter so that the next time

Enter bakery and take a ticket.

sequence_enter() is invoked, the following sequence

 

 

 

number will be returned

 

 

 

 

2

sequence_wait() compares its sequence number with the

Wait in line for the "Now Serving" sign to

absolute.exit, and context swaps until they are the same.

match your ticket.

 

 

 

 

3

Having gotten past sequence_wait(), the thread

Get served, keep others in line away from

processes the critical region.

counter.

 

 

 

 

 

sequence_exit() increments absolute.exit to let the next

Exit bakery, "Now Serving..." sign gets

4

incremented to let next customer to

sequence number past sequence_wait().

 

counter.

 

 

 

 

 

4.5.2.1Example

#define MY_SEQUENCE_HANDLE my_seq_number, @enter, @one, @exit, @one, 32 sequence_init(MY_SEQUENCE_HANDLE) // initilize global state

while()

<...> // get work in order

sequence_enter(MY_SEQUENCE_HANDLE) // record the order <...> // process non-critical section sequence_wait(MY_SEQUENCE_HANDLE) // wait my turn msgq_send() // process critical section sequence_exit(MY_SEQUENCE_HANDLE) // let the next guy go

4.6Message Queues - msgq.uc

The Message Queue subsystem supports 31-bit messages between microengines. The queues are implemented with circular buffers, typically in scratchpad RAM. The queues are point-to-point, there can be only one sender microengine, and one receiver microengine because the queue indexes are stored privately in microengine registers rather than shared in RAM.

If the sender sends to a full queue, it will return an error so that the sender is able to determine what to do with the unsent message.

The threads within the sender must cooperate and not simultaneously access the same queue. This is typically done by putting the msgq_send() or msgq_receive() inside a critical section.

The message queue handle can specify that receives be either asynchronous or synchronous:

Asynchronous receives (MSGQ_ASYNC) will return after reading what was in the queue, no matter if it was valid or invalid. The invoking thread must look at the invalid bit to decide what to do with the message.

Synchronous receives can either loop internally on receipt of invalid messages (MSGQ_SYNC_POLL), or go to sleep after receiving an invalid message (MSGQ_SYNC_SLEEP). The sender must know to (always) wake up the receiver if MSGQ_SYNC_SLEEP is used.

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Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowATM Receive Microengine Microengine Functional BlocksMicroengine Initialization StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorCRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryEntry Description Buffer Offset Buffer IndexCell data11 Entry Description Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache StructureIP Table Function IP Lookup TableVC Cache API IP Table StructureMtuchange IP Table Management APIRoutetableinit AtmrouteaddRoutedelete EnetrouteaddRtentinfo RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdrSequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call DescriptionExample Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line AnalogyMsgqinitregs Msgqhandle ParametersMsgqinitqueue MsgqsendMsgqreceive RamoptionBuffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management MacrosCounters CountCounter Base Address Global ParametersUse of the Counter Subsystem Counter Index#define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutexvectorenter Mutex VectorsMutexvectorinit MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description