Intel IXP1200 manual Simulation Support Scripts, etc, Limitations, Extending the Example Design

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

7.0Simulation Support (Scripts, etc.)

Simulation support for this example design is provided by using a combination of the Foreign Model DLLs (libraries linked to the Transactor simulator), with interpreted Transactor scripts (.ind files).

The IP Route Table Manager and associated RFC1812 utilities are implemented in the rtm_dll.dll foreign model. The ATM VC table manager and associated utilities are implemented in the atm_utils.dll foreign model. Entry points in these DLLs, such as route_populate() and atm_init() are called from the atm_ether_init.ind Transactor script upon initialization. DLL entry points are also available from the Transactor command line interface. The same utilities are compiled into the atm_utils.o VxWorks kernel module, and are thus available at the VxWorks command prompt.

Some simple C programs are also provided to check the Developer’s Workbench output files for correct output data (i.e. CRC verification for PDUs; and integrity of output stream). See the README.txt file for more details.

8.0Limitations

This design supports the entire ATM VC name space. However, the implementation has 16K buffers, and thus can support simultaneous reassembly of no more than 16K PDUs. The buffer limitation comes from two sources.

•The fixed-length 2KB DRAM buffers must fit in physical memory. 16K 2KB buffers consume 32MB of DRAM.

•The Ethernet Transmit Packetq implementation can address only 16K buffer descriptors.

9.0Extending the Example Design

This example design shows how microcode handles "fast-path" data-plane processing. It queues exception packets to the StrongARM core where they are simply discarded. Customers can supply their own software running on the StrongARM core to process these packets.

•This design supports only AAL5. The ATM receiver with its VC table, and the ATM Transmitter could be modified to support other AALs.

•This design does not support ATM traffic shaping. However, this code could be applied to other configurations where threads are dedicated to traffic shaping.

•This design does not support ATM receive policing, but the ATM receiver could be enhanced to do so.

•Switched Virtual Circuits (SVCs) are not implemented, only Permanent Virtual Circuits (PVCs) are currently implemented.

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Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowMicroengine Functional Blocks Microengine InitializationATM Receive Microengine StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorSoftware Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureIP Lookup Table VC Cache APIIP Table Function IP Table StructureIP Table Management API RoutetableinitMtuchange AtmrouteaddEnetrouteadd RtentinfoRoutedelete RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8ATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdrSequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call DescriptionMessage Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line AnalogyMsgqhandle Parameters MsgqinitqueueMsgqinitregs MsgqsendMsgqreceive Ramoption1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management MacrosCounters CountGlobal Parameters Use of the Counter SubsystemCounter Base Address Counter IndexGlobal Counter Enable and Flags Counter Flags#define Statement Description Counter Group DescriptionPortcounterinc Counters.uc CounterresetCounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutex Vectors MutexvectorinitMutexvectorenter MutexvectorexitProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description
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