Motorola warranty Memory map summary, TMS320C6711D Memory Map Summary

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

memory map summary

Table 2 shows the memory map address ranges of the device. Internal memory is always located at address 0 and can be used as both program and data memory. The configuration registers for the common peripherals are located at the same hex address ranges. The external memory address ranges in the device begin at the address location 0x8000 0000.

Table 2. TMS320C6711D Memory Map Summary

MEMORY BLOCK DESCRIPTION

BLOCK SIZE (BYTES)

HEX ADDRESS RANGE

 

 

 

 

Internal RAM (L2)

64K

0000 0000

– 0000 FFFF

 

 

 

 

Reserved

24M – 64K

0001 0000

– 017F FFFF

 

 

 

 

External Memory Interface (EMIF) Registers

256K

0180 0000

– 0183 FFFF

 

 

 

 

L2 Registers

256K

0184 0000

– 0187 FFFF

 

 

 

 

HPI Registers

256K

0188 0000

– 018B FFFF

 

 

 

McBSP 0 Registers

256K

018C 0000 – 018F FFFF

 

 

 

 

McBSP 1 Registers

256K

0190 0000

– 0193 FFFF

 

 

 

 

Timer 0 Registers

256K

0194 0000

– 0197 FFFF

 

 

 

 

Timer 1 Registers

256K

0198 0000

– 019B FFFF

 

 

 

Interrupt Selector Registers

512

019C 0000 – 019C 01FF

 

 

 

Device Configuration Registers

4

019C 0200 – 019C 0203

Reserved

256K − 516

019C 0204 – 019F FFFF

 

 

 

 

EDMA RAM and EDMA Registers

256K

01A0 0000

– 01A3 FFFF

 

 

 

 

Reserved

768K

01A4 0000

– 01AF FFFF

 

 

 

GPIO Registers

16K

01B0 0000 – 01B0 3FFF

Reserved

480K

01B0 4000

– 01B7 BFFF

 

 

 

PLL Controller Registers

8K

01B7 C000 – 01B7 DFFF

Reserved

4M + 520K

01B7 E000 – 01FF FFFF

 

 

 

QDMA Registers

52

0200 0000 – 0200 0033

 

 

 

 

Reserved

736M – 52

0200 0034

– 2FFF FFFF

 

 

 

 

McBSP 0 Data/Peripheral Data Bus

64M

3000 0000

– 33FF FFFF

 

 

 

 

McBSP 1 Data/Peripheral Data Bus

64M

3400 0000

– 37FF FFFF

 

 

 

Reserved

64M

3800 0000 – 3BFF FFFF

 

 

 

 

Reserved

1G + 64M

3C00 0000

– 7FFF FFFF

 

 

 

 

EMIF CE0†

256M

8000 0000

– 8FFF FFFF

EMIF CE1†

256M

9000 0000

– 9FFF FFFF

EMIF CE2†

256M

A000 0000

– AFFF FFFF

EMIF CE3†

256M

B000 0000

– BFFF FFFF

Reserved

1G

C000 0000

– FFFF FFFF

 

 

 

 

†The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of addressable memory, additional general-purpose output pin or external logic is required.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Contents SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal ClockDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description ST2 ST1DA1 DA2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache RegistersHEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM†Quick DMA Qdma and Pseudo Registers† Edma RegistersHPI Registers PLL Controller RegistersGpio Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description CE0 CE3CE2 CE1General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2Device configurations at device reset Device ConfigurationsCLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsHD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little EndianEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV IPD RSVRSV IPU Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd CvddGND Description Name GDP ZDP Supply Voltage PinsGround Pins VSSVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed RangeDocumentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID PwrdPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt SelectorEdma Selector Edma module and Edma selectorEdma Channels ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or DisabledGDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterMode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsDSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations DvddIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Reset BootmodeIOH Recommended operating conditions‡MIN NOM MAX Unit IOZ Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§Clkin CLKOUT3 GDPA-167Parameter −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −FigureAWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE †AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE†CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr EclkoutCEx BE30 EA212 MRS value ED310 MRS EclkoutHold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Eclkout Busreq Busreq TimingCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 HstrobeHCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has †HD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resyncBit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDPQty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak TempSeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice
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