Motorola TMS320C6711D Power-supply sequencing, Characteristics of the Power-Down Modes, PD1

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

Table 33. Characteristics of the Power-Down Modes

PRWD FIELD

POWER-DOWN

WAKE-UP METHOD

EFFECT ON CHIP’S OPERATION

(BITS 15−10)

MODE

 

 

 

 

 

 

000000

No power-down

—

—

 

 

 

 

001001

PD1

Wake by an enabled interrupt

CPU halted (except for the interrupt logic)

Power-down mode blocks the internal clock inputs at the

 

 

 

 

 

Wake by an enabled or

boundary of the CPU, preventing most of the CPU’s logic from

010001

PD1

switching. During PD1, EDMA transactions can proceed

non-enabled interrupt

 

 

between peripherals and internal memory.

 

 

 

 

 

 

 

 

 

 

Output clock from PLL is halted, stopping the internal clock

 

PD2†

 

structure from switching and resulting in the entire chip being

011010

Wake by a device reset

halted. All register and internal RAM contents are preserved. All

 

 

 

functional I/O “freeze” in the last state when the PLL clock is

 

 

 

turned off.

 

 

 

 

 

 

 

Input clock to the PLL stops generating clocks. All register and

 

 

 

internal RAM contents are preserved. All functional I/O “freeze” in

011100

PD3†

Wake by a device reset

the last state when the PLL clock is turned off. Following reset, the

PLL needs time to re-lock, just as it does following power-up.

 

 

 

 

 

 

Wake-up from PD3 takes longer than wake-up from PD2 because

 

 

 

the PLL needs to be re-locked, just as it does following power-up.

 

 

 

 

All others

Reserved

—

—

†When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications.

The device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit in the PLLCSR register. With this enhanced functionality come some additional considerations when entering power-down modes.

The power-down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the device. However, if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input (CLKIN). Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective.

Make sure that the PLL is enabled by writing a “1” to PLLEN bit (PLLCSR.0) before writing to either PD3 (CSR.11) or PD2 (CSR.10) to enter a power-down mode.

power-supply sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage.

system-level design considerations

System-level design considerations, such as bus contention, may require supply sequencing to be implemented. The core supply should be powered up prior to (and powered down after) the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board.

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Contents SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†HPI Registers PLL Controller RegistersGpio Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE3 CE2CE1 CE0Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetCLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationIPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12Emif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV IPD RSVRSV IPU Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See NoteDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitGDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations ModePower-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Bootmode ResetIOH Recommended operating conditions‡MIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement InformationTester Pin Electronics Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See FigureClkin CLKOUT3 GDPA-167Parameter Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure AreSetup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310Hold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Busreq Timing Eclkout BusreqCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe HrdyHCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXBit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTPackage thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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