Motorola TMS320C6711D HOLD/HOLDA Timing, Timing requirements for See Figure HOLD/HOLDA cycles†

Page 82

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

 

 

 

 

 

 

 

HOLD/HOLDA TIMING

 

timing requirements for the

 

 

 

 

 

 

 

 

(see Figure 38)

 

HOLD/HOLDA cycles†

 

 

 

 

 

 

 

 

 

 

 

 

 

GDPA-167

 

 

 

 

 

 

 

 

 

 

 

 

 

ZDPA−167

 

 

NO.

 

 

 

 

 

 

−200

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN MAX

 

 

 

 

 

 

 

 

 

 

3

th(HOLDAL-HOLDL) Hold time,

 

low after

 

 

low

 

E

ns

 

HOLD

HOLDA

 

 

†E = ECLKIN period in ns

 

 

 

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡ (see Figure 38)

 

 

 

 

 

 

 

 

 

GDPA-167

 

 

 

 

 

 

 

 

 

 

ZDPA−167

 

NO.

 

 

 

PARAMETER

−200

 

UNIT

 

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

1

td(HOLDL-EMHZ)

Delay time,

 

low to EMIF Bus high impedance

2E

§

ns

HOLD

2

td(EMHZ-HOLDAL)

Delay time, EMIF Bus high impedance to

 

 

low

0

2E

ns

HOLDA

4

td(HOLDH-EMLZ)

Delay time,

 

high to EMIF Bus low impedance

2E

7E

ns

HOLD

5

td(EMLZ-HOLDAH)

Delay time, EMIF Bus low impedance to

 

 

high

0

2E

ns

HOLDA

†E = ECLKIN period in ns

‡EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

§All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

HOLD

HOLDA

EMIF Bus†

DSP Owns Bus

External Requestor

DSP Owns Bus

Owns Bus

 

 

 

3

 

2

 

5

1

 

4

C67x

 

C67x

†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

Figure 38. HOLD/HOLDA Timing

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Contents SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6711D Processor C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description DA2 ST1DA1 ST2TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register NameEdma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†Gpio Registers PLL Controller RegistersHPI Registers McBSP0 and McBSP1 Registers Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 McBSP1Signal groups description CE1 CE3CE2 CE0CLKOUT2/GP2 GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetBOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationLittle Endian IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control HD12Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV IPU RSVRSV IPD Cvdd Name GDP ZDP Supply Voltage PinsDvdd Supply voltage See NoteVSS Description Name GDP ZDP Supply Voltage PinsGround Pins GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Device Speed Range Device Family Temperature Range Default 0 C to 90 CPrefix TechnologyDocumentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIECPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector EventEdma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX UnitPLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1System-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes ModeDvdd Power-supply decouplingPower-supply design considerations DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode ResetMIN NOM MAX Unit Recommended operating conditions‡IOH Parameter Test Conditions MIN TYP MAX Unit IOZTester Pin Electronics Signal transition levelsParameter Measurement Information Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Timing requirements for Clkin †‡§ PLL Mode Bypass Mode UnitInput and Output Clocks See FigureParameter GDPA-167Clkin CLKOUT3 −200 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −250See −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ AreAOE/SDRAS/SSOE † Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AWE/SDWE/SSWE † ArdyCEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†EA212 ED310 CEx BE30BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureEA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED310 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Dcab EclkoutRefr Eclkout Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310Timing requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Busreq Timing Eclkout BusreqTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Hstrobe HOST-PORT Interface TimingGDPA−167 Hstrobe HrdyHCS Hrdy Has † HasHR/W Hhwil Hstrobe † HCS HR/W Hhwil Hstrobe ‡ HCSHrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Bitn-1 Clks ClkrFSR int ClkxFSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAXClkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Timing requirements for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing TCK TDO TDI/TMS/TRSTThermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical DataMSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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