Motorola TMS320C6711D Reset Timing, Timing requirements for reset†‡ see Figure, CLKMODE0 =

Page 84

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

RESET TIMING

timing requirements for reset†‡ (see Figure 40)

 

 

 

 

 

 

 

 

 

GDPA-167

 

 

 

 

 

 

 

 

 

 

ZDPA−167

 

NO.

 

 

 

 

 

 

 

 

−200

 

UNIT

 

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

1

tw(RST)

Pulse duration,

 

 

 

 

 

 

100

 

ns

RESET

 

 

 

 

 

 

13

tsu(HD)

Setup time, HD boot configuration bits valid before

 

 

high§

2P

 

ns

RESET

 

14

t

Hold time, HD boot configuration bits valid after

 

 

high§

2P

 

ns

RESET

 

 

h(HD)

 

 

 

 

 

 

 

 

 

 

†P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡The PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Software-ProgrammablePhase-Lock Loop (PLL)

Controller Reference Guide (literature number SPRU233).

§The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits consist of: HD[8, 4:3].

switching characteristics over recommended operating conditions during reset(see Figure 40)

 

 

 

 

 

 

 

 

 

 

 

GDPA-167

 

 

 

 

 

 

 

 

 

 

 

 

ZDPA−167

 

NO.

 

PARAMETER

 

 

−200

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

 

 

2

td(RSTH-ZV)

Delay time, external

RESET

high to internal reset

 

CLKMODE0 = 1

 

512 x CLKIN

ns

#

 

 

period

 

 

high and all signal groups valid

 

 

 

 

 

 

 

 

 

 

 

 

 

3

td(RSTL-ECKOL)

Delay time,

RESET

 

 

low to ECLKOUT high impedance

 

0

 

ns

4

td(RSTH-ECKOV)

Delay time,

 

 

 

high to ECLKOUT valid

 

 

6P

ns

RESET

 

 

 

5

td(RSTL-CKO2IV)

Delay time,

 

 

 

low to CLKOUT2 high impedance

 

0

 

ns

RESET

 

 

 

6

td(RSTH-CKO2V)

Delay time,

 

 

 

high to CLKOUT2 valid

 

 

6P

ns

RESET

 

 

 

7

td(RSTL-CKO3L)

Delay time,

 

 

 

low to CLKOUT3 low

 

0

 

ns

RESET

 

 

 

8

td(RSTH-CKO3V)

Delay time,

 

 

 

high to CLKOUT3 valid

 

 

6P

ns

RESET

 

 

 

9

t

Delay time,

 

 

 

low to EMIF Z group high impedance

0

 

ns

RESET

 

 

d(RSTL-EMIFZHZ)

 

 

 

 

 

 

 

 

 

 

 

 

10

td(RSTL-EMIFLIV)

Delay time,

 

 

low to EMIF low group (BUSREQ) invalid

0

 

ns

RESET

 

11

td(RSTL-Z1HZ)

Delay time,

 

 

 

low to Z group 1 high impedance

 

0

 

ns

RESET

 

 

12

t

Delay time,

 

 

 

low to Z group 2 high impedance

 

0

 

ns

RESET

 

 

 

d(RSTL-Z2HZ)

 

 

 

 

 

 

 

 

 

 

 

 

P = 1/CPU clock frequency in ns.

Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For

example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while internal reset is asserted.

#The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET is deasserted, the actual delay time may vary.

EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and

 

HOLDA

EMIF low group consists of: BUSREQ

Z group 1 consists of:

CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.

Z group 2 consists of:

All other HPI and GPIO signals

84

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Contents SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHPI Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE3 CE2CE1 CE0Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetConfiguration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationIPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV RSV IPURSV IPD Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See NoteDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations ModePower-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode ResetRecommended operating conditions‡ MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement InformationTester Pin Electronics Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See FigureGDPA-167 ParameterClkin CLKOUT3 Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure AreSetup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdySetup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureRead Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Busreq Timing Eclkout BusreqReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe HrdyHCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXMASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTPackage thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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