Motorola TMS320C6711D warranty Interrupt Selector Registers, Device Registers, Edma Parameter RAM†

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

peripheral register descriptions (continued)

Table 5. Interrupt Selector Registers

	HEX ADDRESS RANGE	ACRONYM	REGISTER NAME	COMMENTS

	019C 0000	MUXH	Interrupt multiplexer high	Selects which interrupts drive CPU interrupts 10−15
	019C 0000	MUXH	Interrupt multiplexer high	(INT10−INT15)
				(INT10−INT15)

	019C 0004	MUXL	Interrupt multiplexer low	Selects which interrupts drive CPU interrupts 4−9
	019C 0004	MUXL	Interrupt multiplexer low	(INT04−INT09)
				(INT04−INT09)

	019C 0008	EXTPOL	External interrupt polarity	Sets the polarity of the external interrupts
	019C 0008	EXTPOL	External interrupt polarity	(EXT_INT4−EXT_INT7)
				(EXT_INT4−EXT_INT7)

	019C 000C − 019F FFFF	−	Reserved

				Table 6. Device Registers

HEX ADDRESS RANGE			ACRONYM		REGISTER DESCRIPTION

						This register allows the user control of the EMIF input
019C 0200			DEVCFG	Device Configuration		clock source. For more detailed information on the
019C 0200			DEVCFG	Device Configuration		device configuration register, see the Device
						device configuration register, see the Device
						Configurations section of this data sheet.

019C 0204	− 019F FFFF		−	Reserved

						Identifies which CPU and defines the silicon revision of
						the CPU. This register also offers the user control of
N/A			CSR	CPU Control Status Register		device operation.
N/A			CSR	CPU Control Status Register		For more detailed information on the CPU Control
						For more detailed information on the CPU Control
						Status Register, see the CPU CSR Register
						Description section of this data sheet.
				Table 7. EDMA Parameter RAM†

HEX ADDRESS RANGE			ACRONYM			REGISTER NAME

01A0 0000	− 01A0	0017	−	Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event

01A0 0018	− 01A0 002F		−	Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event

01A0 0030	− 01A0	0047	−	Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event

01A0 0048	− 01A0 005F		−	Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event

01A0 0060	− 01A0	0077	−	Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event

01A0 0078	− 01A0 008F		−	Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event

01A0 0090	− 01A0 00A7		−	Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event

01A0 00A8	− 01A0 00BF		−	Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event

01A0 00C0	− 01A0 00D7		−	Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event

01A0 00D8	− 01A0 00EF		−	Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event

01A0 00F0 − 01A0 00107			−	Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event

01A0 0108 − 01A0 011F			−	Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event

01A0 0120	− 01A0 0137		−	Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event

01A0 0138	− 01A0 014F		−	Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event

01A0 0150	− 01A0 0167		−	Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event

01A0 0168	− 01A0 017F		−	Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event

01A0 0180	− 01A0 0197		−	Reload/link parameters for Event 0−15

01A0 0198 − 01A0 01AF			−	Reload/link parameters for Event 0−15

	...			...

01A0 07E0 − 01A0 07F7			−	Reload/link parameters for Event 0−15

01A0 07F8	− 01A0 07FF		−	Scratch pad area (2 words)

†The device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.

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Contents SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description Characteristics of the C6711D Processor Device characteristicsHardware Features Internal Clock C6711DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1 DA2 ST2TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersHPI Registers HEX Address Range Acronym Register Name Comments Timer Timer 0 and Timer 1 RegistersMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE2 CE3CE1 CE0GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 GpioCLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice configurations at device reset Device ConfigurationsBOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsUsed for transfer of data, address, and control IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPILittle Endian HD12Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV IPU RSVRSV IPD Dvdd Name GDP ZDP Supply Voltage PinsCvdd Supply voltage See NoteGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Prefix Device Family Temperature Range Default 0 C to 90 CDevice Speed Range TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIECPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma Channels Edma module and Edma selectorEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitPLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingSystem-level design considerations ModePower-supply design considerations Power-supply decouplingDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset BootmodeMIN NOM MAX Unit Recommended operating conditions‡IOH IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levelsTester Pin Electronics Output Under Test= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Input and Output Clocks PLL Mode Bypass Mode UnitTiming requirements for Clkin †‡§ See FigureParameter GDPA-167Clkin CLKOUT3 GDPA-167 ZDPA−167 Timing requirements for ECLKIN† see Figure−200 −250Timing requirements for asynchronous memory cycles†‡§ Asynchronous Memory TimingSee −Figure AreCEx BE30 EA212 Address ED310 Read Data Setup = Strobe = Not ReadyAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdyCEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingEA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA2113 Write EclkoutEA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Deac EclkoutRefr Eclkout CEx BE30 EA212 EA12 ED310CEx BE30 EA212 MRS value ED310 MRS EclkoutTiming requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Eclkout Busreq Busreq TimingTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI GDPA−167 HOST-PORT Interface TimingHstrobe Hstrobe HrdyHCS Hrdy HR/W Hhwil Hstrobe † HCS HasHas † HR/W Hhwil Hstrobe ‡ HCSHrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXClkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Jtag TEST-PORT Timing DTCKL-TDOV Delay time, TCK low to TDO validTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTThermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice