
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
device characteristics
Table 1 provides an overview of the C6711D DSP. The table shows significant features of the device, including the capacity of
Table 1. Characteristics of the C6711D Processor
HARDWARE FEATURES |
| INTERNAL CLOCK | C6711D | |
| SOURCE |
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| EMIF | ECLKIN |
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| SYSCLK3 or ECLKIN | 1 | ||
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| EDMA | CPU clock frequency | 1 | |
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| HPI | CPU/2 clock frequency |
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Peripherals | SYSCLK2 | 1 | ||
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McBSPs | CPU/2 clock frequency |
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| SYSCLK2 | 2 | ||
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| CPU/4 clock frequency | — | ||
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| 1/2 of SYSCLK2 | 2 | ||
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| GPIO Module | SYSCLK2 | 1 | |
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| Size (Bytes) |
| 72K | |
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| (L1P) Cache | ||
Organization |
| 4KB L1 Data (L1D) Cache | ||
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| 64KB Unified Mapped | |
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| RAM/Cache (L2) | |
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CPU ID+ | Control Status Register (CSR.[31:16]) | 0x0203 | ||
CPU Rev ID | ||||
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Frequency | MHz |
| 167, 200, 250 | |
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| 4 ns | |
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| 5 ns (C6711DGDP−200 | |
Cycle Time | ns |
| and C6711DZDP−200) | |
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| 6 ns (C6711DGDPA−167 | |
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| and C6711DZDPA−167) | |
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| Core (V) |
| 1.20† | |
Voltage |
| 1.4 (−250) | ||
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| I/O (V) |
| 3.3 | |
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PLL Options | CLKIN frequency multiplier | − | ||
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| Prescaler |
| /1, /2, /3, ..., /32 | |
Clock Generator Options | Multiplier |
| x4, x5, x6, ..., x25 | |
| Postscaler |
| /1, /2, /3, ..., /32 | |
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BGA Package | 27 x 27 mm |
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| (GDP and ZDP)§ | |||
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Process Technology | ∝m |
| 0.13 ∝m | |
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Product Status |
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Product Preview (PP) |
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| PD‡ | |
Advance Information (AI) |
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Production Data (PD) |
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†These values are compatible with existing 1.26−V designs.
‡PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
§The ZDP package devices are supported in the same speed grades as the GDP package devices (available upon request).
C6000 is a trademark of Texas Instruments.
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