Motorola TMS320C6711D warranty Parameter Test Conditions MIN TYP MAX Unit, Ioz

Page 63

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

electrical characteristics over recommended ranges of supply voltage and operating case temperature† (unless otherwise noted)

 

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

 

VOH

High-level output

All signals except CLKS1 and

DVDD = MIN, IOH = MAX

2.4

 

 

V

voltage

DR1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-level output

All signals except CLKS1 and

 

 

 

0.4

 

VOL

DR1

DVDD = MIN, IOL = MAX

 

 

V

voltage

 

 

 

 

 

 

 

 

CLKS1 and DR1

 

 

 

0.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All signals except CLKS1 and

 

 

 

±170

uA

II

Input current

DR1

VI = VSS to DVDD

 

 

 

 

 

 

 

 

CLKS1 and DR1

 

 

 

±10

uA

 

 

 

 

 

 

 

 

 

Off-state output

All signals except CLKS1 and

 

 

 

±170

uA

IOZ

DR1

VO = DVDD or 0 V

 

 

current

 

 

 

 

 

CLKS1 and DR1

 

 

 

±10

uA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GDP, CVDD = 1.4-V,

 

810

 

 

 

 

 

CPU clock = 250 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GDP/ZDP, CVDD =

 

 

 

 

I

Core supply current‡

 

1.26-V, CPU clock =

 

560

 

mA

 

 

 

 

 

DD2V

 

 

200 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GDPA/ZDPA, CVDD =

 

 

 

 

 

 

 

1.26-V, CPU clock =

 

475

 

 

 

 

 

167 MHz

 

 

 

 

 

 

 

 

 

 

 

 

I

I/O supply current‡

 

DVDD = 3.3-V, EMIF

 

75

 

mA

DD3V

 

 

speed = 100 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ci

Input capacitance

 

 

 

 

7

pF

Co

Output capacitance

 

 

 

 

7

pF

†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

‡For this device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

High-DSP-Activity Model:

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

Low-DSP-Activity Model:

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power Consumption Summary application report (literature number SPRA889A).

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Contents SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal ClockDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description ST2 ST1DA1 DA2Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache RegistersHEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM†Quick DMA Qdma and Pseudo Registers† Edma RegistersPLL Controller Registers Gpio RegistersHPI Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description CE0 CE3CE2 CE1General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2Device configurations at device reset Device ConfigurationsConfiguration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsHD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little EndianOnly one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV RSV IPURSV IPD Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd CvddGND Description Name GDP ZDP Supply Voltage PinsGround Pins VSSVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed RangeDocumentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID PwrdCPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt SelectorEdma module and Edma selector Edma ChannelsEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or DisabledClock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterMode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsDSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations DvddIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset BootmodeRecommended operating conditions‡ MIN NOM MAX UnitIOH IOZ Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§GDPA-167 ParameterClkin CLKOUT3 −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −FigureAWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE †Setup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingRead Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE†CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr EclkoutCEx BE30 EA212 MRS value ED310 MRS EclkoutHOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Eclkout Busreq Busreq TimingReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 HstrobeHCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has †HD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resyncMASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDPQty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak TempSeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice
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