Motorola TMS320C6711D warranty 1 ¶

Page 91

SPRS292 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 46)

 

 

 

 

 

GDPA−167

 

 

 

 

 

 

 

ZDPA−167

 

 

NO.

 

 

 

 

−200

 

UNIT

 

 

 

 

 

−250

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

2

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

 

2P§

 

ns

3

t

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

0.5 *t

 

−1

 

ns

 

w(CKRX)

 

 

c(CKRX)

 

 

 

5

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR int

 

 

9

 

ns

 

 

 

 

 

CLKR ext

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR int

 

 

6

 

ns

 

 

 

 

 

CLKR ext

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR int

 

 

8

 

ns

 

 

 

 

 

CLKR ext

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR int

 

 

3

 

ns

 

 

 

 

 

CLKR ext

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX int

 

 

9

 

ns

 

 

 

 

 

CLKX ext

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX int

 

 

6

 

ns

 

 

 

 

 

CLKX ext

 

 

3

 

 

 

 

 

 

 

 

†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

§The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =

33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Contents SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal ClockDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description ST2 ST1DA1 DA2TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache RegistersHEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM†Quick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersHPI Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description CE0 CE3CE2 CE1General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2Device configurations at device reset Device ConfigurationsBOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsHD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little EndianDecoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV IPU RSVRSV IPD Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd CvddGND Description Name GDP ZDP Supply Voltage PinsGround Pins VSSVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed RangeDocumentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID PwrdCPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt SelectorEdma Channels Edma module and Edma selectorEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or DisabledPLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterMode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsDSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations DvddIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset BootmodeMIN NOM MAX Unit Recommended operating conditions‡IOH IOZ Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§Parameter GDPA-167Clkin CLKOUT3 −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −FigureAWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE †CEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingEA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE†CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr EclkoutCEx BE30 EA212 MRS value ED310 MRS EclkoutTiming requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Eclkout Busreq Busreq TimingTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 Hstrobe HCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has †Hrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resyncClkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDPQty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak TempSeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice
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