Motorola TMS320C6711D warranty Cache configuration Ccfg register description, L2MODE

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

cache configuration (CCFG) register description

The device includes an enhancement to the cache configuration (CCFG) register. A “P” bit (CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2 memory.

For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory accesses blocked, see the TMS320C6711/TMS320C6711B/TMS320C6711C/TMS320C6711D Digital Signal Processors Silicon Errata (literature number SPRZ173K or later).

31

30

10

9

8

7

3

2

0

 

 

 

 

 

 

 

 

 

P

Reserved

 

IP

ID

Reserved

 

 

L2MODE

 

 

 

 

 

 

 

 

 

R/W-0

R-x

 

W-0

W-0

R-0 0000

 

 

R/W-000

 

 

 

 

 

 

 

 

 

Legend: R = Readable; R/W = Readable/Writeable; -n= value after reset; -x = undefined value after reset

Figure 7. Cache Configuration Register (CCFG)

 

 

 

 

Table 19. CCFG Register Bit Field Description

 

 

 

 

 

 

BIT #

NAME

 

 

 

DESCRIPTION

 

 

 

 

 

L1D requestor priority to L2 bit.

31

P

P

=

0: L1D requests to L2 higher priority than TC requests

 

 

P

=

1: TC requests to L2 higher priority than L1D requests

 

 

 

30:10

Reserved

Reserved. Read-only, writes have no effect.

 

 

 

 

 

 

Invalidate L1P bit.

 

9

IP

0

=

Normal L1P operation

 

 

 

1

=

All L1P lines are invalidated

 

 

 

 

 

 

Invalidate L1D bit.

 

8

ID

0

=

Normal L1D operation

 

 

 

1

=

All L1D lines are invalidated

 

 

 

7:3

Reserved

Reserved. Read-only, writes have no effect.

 

 

 

 

 

L2 operation mode bits (L2MODE).

 

 

000b

= L2 Cache disabled (All SRAM mode) [64K SRAM]

2:0

L2MODE

001b

= 1-way Cache (16K

L2 Cache) / [48K SRAM]

010b

= 2-way Cache (32K

L2 Cache) / [32K SRAM]

 

 

 

 

011b

= 3-way Cache (48K

L2 Cache) / [16K SRAM]

 

 

111b

= 4-way Cache (64K

L2 Cache) / [no SRAM]

 

 

All others Reserved

 

42

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Contents SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6711D Processor C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description DA2 ST1DA1 ST2Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register NameEdma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHPI Registers McBSP0 and McBSP1 Registers Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 McBSP1Signal groups description CE1 CE3CE2 CE0CLKOUT2/GP2 GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetConfiguration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationLittle Endian IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control HD12Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV RSV IPURSV IPD Cvdd Name GDP ZDP Supply Voltage PinsDvdd Supply voltage See NoteVSS Description Name GDP ZDP Supply Voltage PinsGround Pins GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Device Speed Range Device Family Temperature Range Default 0 C to 90 CPrefix TechnologyDocumentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1System-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes ModeDvdd Power-supply decouplingPower-supply design considerations DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode ResetRecommended operating conditions‡ MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZTester Pin Electronics Signal transition levelsParameter Measurement Information Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Timing requirements for Clkin †‡§ PLL Mode Bypass Mode UnitInput and Output Clocks See FigureGDPA-167 ParameterClkin CLKOUT3 −200 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −250See −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ AreAOE/SDRAS/SSOE † Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AWE/SDWE/SSWE † ArdySetup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†EA212 ED310 CEx BE30BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureRead Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED310 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Dcab EclkoutRefr Eclkout Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Busreq Timing Eclkout BusreqReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Hstrobe HOST-PORT Interface TimingGDPA−167 Hstrobe HrdyHCS Hrdy Has † HasHR/W Hhwil Hstrobe † HCS HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Bitn-1 Clks ClkrFSR int ClkxFSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAXMASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Timing requirements for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing TCK TDO TDI/TMS/TRSTThermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical DataMSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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