Motorola TMS320C6711D Peripheral register descriptions, Emif Registers, L2 Cache Registers

Page 12

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

peripheral register descriptions

Table 3 through Table 14 identify the peripheral registers for the device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).

 

 

Table 3. EMIF Registers

 

 

 

 

 

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

 

 

 

 

 

0180 0000

GBLCTL

EMIF global control

 

 

 

 

 

0180 0004

CECTL1

EMIF CE1 space control

 

 

 

 

 

0180 0008

CECTL0

EMIF CE0 space control

 

 

 

 

 

0180 000C

−

Reserved

 

 

 

 

 

0180 0010

CECTL2

EMIF CE2 space control

 

 

 

 

 

0180 0014

CECTL3

EMIF CE3 space control

 

 

 

 

 

0180 0018

SDCTL

EMIF SDRAM control

 

 

 

 

 

0180 001C

SDTIM

EMIF SDRAM refresh control

 

 

 

 

 

0180 0020

SDEXT

EMIF SDRAM extension

 

 

 

 

 

0180 0024 − 0183 FFFF

−

Reserved

 

 

 

Table 4. L2 Cache Registers

 

 

 

 

 

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

 

 

 

 

 

0184 0000

CCFG

Cache configuration register

 

 

 

 

 

0184 4000

L2WBAR

L2 writeback base address register

 

 

 

 

 

0184 4004

L2WWC

L2 writeback word count register

 

 

 

 

 

0184 4010

L2WIBAR

L2 writeback-invalidate base address register

 

 

 

 

 

0184 4014

L2WIWC

L2 writeback-invalidate word count register

 

 

 

 

 

0184 4020

L1PIBAR

L1P invalidate base address register

 

 

 

 

 

0184 4024

L1PIWC

L1P invalidate word count register

 

 

 

 

 

0184 4030

L1DWIBAR

L1D writeback-invalidate base address register

 

 

 

 

 

0184 4034

L1DWIWC

L1D writeback-invalidate word count register

 

 

 

 

 

0184 5000

L2WB

L2 writeback all register

 

 

 

 

 

0184 5004

L2WBINV

L2 writeback-invalidate all register

 

 

 

 

 

0184 8200

MAR0

Controls CE0 range 8000 0000 − 80FF FFFF

 

 

 

 

 

0184 8204

MAR1

Controls CE0 range 8100 0000 − 81FF FFFF

 

 

 

 

 

0184 8208

MAR2

Controls CE0 range 8200 0000 − 82FF FFFF

 

 

 

 

 

0184 820C

MAR3

Controls CE0 range 8300 0000 − 83FF FFFF

 

 

 

 

 

0184 8240

MAR4

Controls CE1 range 9000 0000 − 90FF FFFF

 

 

 

 

 

0184 8244

MAR5

Controls CE1 range 9100 0000 − 91FF FFFF

 

 

 

 

 

0184 8248

MAR6

Controls CE1 range 9200 0000 − 92FF FFFF

 

 

 

 

 

0184 824C

MAR7

Controls CE1 range 9300 0000 − 93FF FFFF

 

 

 

 

 

0184 8280

MAR8

Controls CE2 range A000 0000 − A0FF FFFF

 

 

 

 

 

0184 8284

MAR9

Controls CE2 range A100 0000 − A1FF FFFF

 

 

 

 

 

0184 8288

MAR10

Controls CE2 range A200 0000 − A2FF FFFF

 

 

 

 

 

0184 828C

MAR11

Controls CE2 range A300 0000 − A3FF FFFF

 

 

 

 

 

0184 82C0

MAR12

Controls CE3 range B000 0000 − B0FF FFFF

 

 

 

 

 

0184 82C4

MAR13

Controls CE3 range B100 0000 − B1FF FFFF

 

 

 

 

 

0184 82C8

MAR14

Controls CE3 range B200 0000 − B2FF FFFF

 

 

 

 

 

0184 82CC

MAR15

Controls CE3 range B300 0000 − B3FF FFFF

 

 

 

 

 

0184 82D0 − 0187 FFFF

−

Reserved

 

 

 

 

 

 

 

 

 

12

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Contents SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHPI Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE3 CE2CE1 CE0Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetConfiguration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationIPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV RSV IPURSV IPD Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See NoteDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations ModePower-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode ResetRecommended operating conditions‡ MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement InformationTester Pin Electronics Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See FigureGDPA-167 ParameterClkin CLKOUT3 Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure AreSetup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdySetup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureRead Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Busreq Timing Eclkout BusreqReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe HrdyHCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXMASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTPackage thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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