Motorola TMS320C6711D warranty Multichannel Buffered Serial Port Timing, Parameter

Page 92

SPRS292 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 46)

 

 

 

 

GDPA−167

 

 

 

 

 

ZDPA−167

 

NO.

 

PARAMETER

 

−200

 

UNIT

 

 

 

 

−250

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

1

td(CKSH-CKRXH)

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from

1.8

10

ns

CLKS input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

t

Cycle time, CLKR/X

CLKR/X int

2P§¶

 

ns

 

c(CKRX)

 

 

 

 

 

3

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C − 1 #

C + 1#

ns

4

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

−2

3

ns

9

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX int

−2

3

ns

 

 

 

CLKX ext

2

9

 

 

 

 

 

 

 

 

 

 

 

12

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

CLKX int

−1

4

ns

CLKX high

CLKX ext

1.5

10

13

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX int

−3.2 + D1

4 + D2

ns

CLKX ext

0.5 + D1

10+ D2

 

 

Delay time, FSX high to DX valid

FSX int

−1

7.5

 

 

 

 

 

14

td(FXH-DXV)

ONLY applies when in data

 

 

 

ns

FSX ext

2

11.5

 

 

 

 

 

delay 0 (XDATDLY = 00b) mode

 

 

 

 

 

 

 

†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡ Minimum delay times also represent minimum output hold times.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =

33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM

=0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

#C = H or L

S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)

=sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H =

CLKX high pulse width

= (CLKGDV/2 + 1) * S if CLKGDV is even

 

 

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

 

 

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).

Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0

If DXENA = 1, then D1 = 2P, D2 = 4P

92

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Contents SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†HPI Registers PLL Controller RegistersGpio Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE3 CE2CE1 CE0Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetCLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationIPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12Emif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV IPD RSVRSV IPU Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See NoteDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitGDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations ModePower-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Bootmode ResetIOH Recommended operating conditions‡MIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement InformationTester Pin Electronics Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See FigureClkin CLKOUT3 GDPA-167Parameter Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure AreSetup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310Hold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Busreq Timing Eclkout BusreqCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe HrdyHCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXBit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTPackage thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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