Motorola TMS320C6711D warranty McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp =

Page 98

SPRS292 − OCTOBER 2005

switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 50)

 

 

 

 

GDPA−167

 

 

 

 

 

 

ZDPA−167

 

 

NO.

 

PARAMETER

 

 

−200

 

UNIT

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

MASTER§

SLAVE

 

 

 

 

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

1

th(CKXH-FXL)

Hold time, FSX low

T − 2

T + 3

 

 

ns

after CLKX high

 

 

2

td(FXL-CKXL)

Delay time, FSX low to CLKX low#

H − 2

H + 3

 

 

ns

3

td(CKXL-DXV)

Delay time, CLKX low to DX valid

−3

4

6P + 2

10P + 17

ns

6

tdis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

H − 2

H + 3

 

 

ns

CLKX high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

tdis(FXH-DXHZ)

Disable time, DX high impedance following last data bit from FSX

 

 

2P + 3

6P + 17

ns

high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

td(FXL-DXV)

Delay time, FSX low to DX valid

 

 

4P + 2

8P + 17

ns

†P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)

=Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =

CLKX period = (1 + CLKGDV) * S

H =

CLKX high pulse width

= (CLKGDV/2 + 1) * S if CLKGDV is even

 

 

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even

=(CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

CLKX

 

 

 

 

 

 

1

2

 

 

 

FSX

 

 

 

 

 

 

 

7

 

 

 

 

6

8

3

 

 

DX

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

 

 

4

5

 

 

 

 

 

 

 

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

98

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Page 97 Page 99
Image 98
Page 97 Page 99
Contents SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6711D Processor C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description DA2 ST1DA1 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register NameEdma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†HPI Registers PLL Controller RegistersGpio Registers McBSP0 and McBSP1 Registers Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 McBSP1Signal groups description CE1 CE3CE2 CE0CLKOUT2/GP2 GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetCLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationLittle Endian IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control HD12Emif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV IPD RSVRSV IPU Cvdd Name GDP ZDP Supply Voltage PinsDvdd Supply voltage See NoteVSS Description Name GDP ZDP Supply Voltage PinsGround Pins GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Device Speed Range Device Family Temperature Range Default 0 C to 90 CPrefix TechnologyDocumentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX UnitGDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1System-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes ModeDvdd Power-supply decouplingPower-supply design considerations DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Bootmode ResetIOH Recommended operating conditions‡MIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZTester Pin Electronics Signal transition levelsParameter Measurement Information Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure Timing requirements for Clkin †‡§ PLL Mode Bypass Mode UnitInput and Output Clocks See FigureClkin CLKOUT3 GDPA-167Parameter −200 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −250See −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ AreAOE/SDRAS/SSOE † Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AWE/SDWE/SSWE † ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†EA212 ED310 CEx BE30BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 EA12 ED310 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Dcab EclkoutRefr Eclkout Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310Hold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Busreq Timing Eclkout BusreqCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Hstrobe HOST-PORT Interface TimingGDPA−167 Hstrobe HrdyHCS Hrdy Has † HasHR/W Hhwil Hstrobe † HCS HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing Bitn-1 Clks ClkrFSR int ClkxFSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAXBit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Timing requirements for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing TCK TDO TDI/TMS/TRSTThermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical DataMSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
Top Page Image Contents