SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
signal groups description
CLKIN
CLKOUT3
CLKOUT2†
CLKMODE0
PLLHV
TMS
TDO
TDI
TCK
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
Clock/PLL
IEEE Standard
1149.1
(JTAG)
Emulation
Control/Status
Reset and Interrupts
Reserved
RESET NMI EXT_INT7‡ EXT_INT6‡ EXT_INT5‡ EXT_INT4‡
RSV
RSV
RSV
•
•
•
RSV
RSV
RSV
16
HD[15:0]
HCNTL0
HCNTL1
HHWIL
Data
Register Select
Select
HPI
Control
HAS
HR/W
HCS
HDS1
HDS2
HRDY HINT
†For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin. Default function is CLKOUT2. To use this pin as GPIO, the GP2EN bit in the GPEN register and the GP2DIR bit in the GPDIR register must be properly configured.
‡For this device, the external interrupts (EXT_INT[7−4]) go through the
Figure 3. CPU (DSP Core) and Peripheral Signals
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