Motorola TMS320C6711D Timer 0 and Timer 1 Registers, McBSP0 and McBSP1 Registers, McBSP0 McBSP1

Page 16

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

peripheral register descriptions (continued)

Table 13. Timer 0 and Timer 1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

 

 

TIMER 0

TIMER 1

 

 

 

 

 

 

 

 

 

 

 

 

Determines the operating

0194 0000

0198 0000

CTLx

Timer x control register

mode of the timer, monitors the

timer status, and controls the

 

 

 

 

 

 

 

 

function of the TOUT pin.

 

 

 

 

 

 

 

 

 

Contains the number of timer

0194 0004

0198 0004

PRDx

Timer x period register

input clock cycles to count.

This number controls the

 

 

 

 

 

 

 

 

TSTAT signal frequency.

 

 

 

 

 

0194 0008

0198 0008

CNTx

Timer x counter register

Contains the current value of

the incrementing counter.

 

 

 

 

 

 

 

 

 

0194 000C − 0197 FFFF

0198 000C − 019B FFFF

−

Reserved

−

 

 

 

 

 

Table 14. McBSP0 and McBSP1 Registers

 

HEX ADDRESS RANGE

ACRONYM

REGISTER DESCRIPTION

 

 

 

McBSP0

McBSP1

 

 

 

 

 

 

 

 

 

 

 

McBSPx data receive register via Configuration Bus

018C

0000

0190 0000

DRRx

The CPU and EDMA controller can only read this register;

 

 

 

 

 

 

 

 

they cannot write to it.

 

 

 

 

3000 0000 − 33FF FFFF

3400 0000 − 37FF FFFF

DRRx

McBSPx data receive register via Peripheral Data Bus

 

 

 

 

 

018C

0004

0190 0004

DXRx

McBSPx data transmit register via Configuration Bus

 

 

 

 

3000 0000 − 33FF FFFF

3400 0000 − 37FF FFFF

DXRx

McBSPx data transmit register via Peripheral Data Bus

 

 

 

 

 

018C

0008

0190 0008

SPCRx

McBSPx serial port control register

 

 

 

 

018C 000C

0190 000C

RCRx

McBSPx receive control register

 

 

 

 

 

018C

0010

0190 0010

XCRx

McBSPx transmit control register

 

 

 

 

 

018C

0014

0190 0014

SRGRx

McBSPx sample rate generator register

 

 

 

 

 

018C

0018

0190 0018

MCRx

McBSPx multichannel control register

 

 

 

 

018C 001C

0190 001C

RCERx

McBSPx receive channel enable register

 

 

 

 

 

018C

0020

0190 0020

XCERx

McBSPx transmit channel enable register

 

 

 

 

 

018C

0024

0190 0024

PCRx

McBSPx pin control register

 

 

 

 

018C 0028 − 018F FFFF

0190 0028 − 0193 FFFF

−

Reserved

16

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Contents SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†Gpio Registers PLL Controller RegistersHPI Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE3 CE2CE1 CE0Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice Configurations Device configurations at device resetBOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag EmulationIPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleRSV IPU RSVRSV IPD Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See NoteDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDPIN Signal TYPE† Description Name GDP ZDP Ground Pins VSSDescription Name GDP ZDP Ground Pins VSS GNDSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIECPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitPLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations ModePower-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode ResetMIN NOM MAX Unit Recommended operating conditions‡IOH Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement InformationTester Pin Electronics Output Under TestAC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See FigureParameter GDPA-167Clkin CLKOUT3 Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure AreSetup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdyCEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles†CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see FigureEA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310MRS Eclkout CEx BE30 EA212 MRS value ED310Timing requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Busreq Timing Eclkout BusreqTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe HrdyHCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCSHrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXClkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTPackage thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice
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