Motorola TMS320C6711D Configuration GDP/ZDP Functional Description PIN, Bootmode‡, CLKMODE0

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

Table 15. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0)†

CONFIGURATION

GDP/ZDP

 

 

FUNCTIONAL DESCRIPTION

PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF Big Endian mode correctness

 

 

 

 

(EMIFBE)

 

 

 

0

–

The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of

 

 

 

 

the endianess mode (Little/Big Endian).

 

 

1

−

In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be present on the

HD12‡

 

 

 

ED[7:0] side of the bus.

C15

 

 

In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present on the

 

 

 

 

ED[31:24] side of the bus [default].

 

 

EMIF Big Endian mode correctness is not supported on the C6711/11B/11C device.

 

 

This new functionality does not affect systems using the current default value of HD12=1. For

 

 

more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode

 

 

Correctness portion of this data sheet.

 

 

 

HD8‡

 

Device Endian mode (LEND)

B17

0

–

System operates in Big Endian mode

 

 

1

−

System operates in Little Endian mode (default)

 

 

 

 

 

Bootmode Configuration Pins (BOOTMODE)

 

 

00 –

HPI boot/Emulation boot

 

 

01 –

CE1 width 8-bit, Asynchronous external ROM boot with default

 

 

 

 

timings (default mode)

HD[4:3]

C19, C20

10 −

CE1 width 16-bit, Asynchronous external ROM boot with default

(BOOTMODE)‡

 

 

timings

 

 

 

 

 

11 −

CE1 width 32-bit, Asynchronous external ROM boot with default

 

 

 

 

timings

 

 

For more detailed information on these bootmode configurations, see the bootmode section of

 

 

this data sheet.

 

 

 

 

 

Clock generator input clock source select

 

 

0

–

Reserved. Do not use.

CLKMODE0

C4

1

−

CLKIN square wave [default]

 

 

 

 

 

 

 

For proper device operation, this pin must be either left unconnected or externally pulled up

 

 

with a 1-kΩresistor.

†All other HD pins or HD [15:13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs or IPDs). For proper device operation of the HD [14, 13, 11:9, 7, 1, 0], do not oppose these pins with external pullups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.

‡To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-k Ω pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Contents SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Characteristics of the C6711D Processor Device characteristicsHardware Features Internal Clock C6711DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1DA2 ST2Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersPLL Controller Registers Gpio RegistersHPI Registers HEX Address Range Acronym Register Name Comments Timer Timer 0 and Timer 1 RegistersMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE2 CE3CE1 CE0GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 GpioCLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice configurations at device reset Device ConfigurationsConfiguration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsUsed for transfer of data, address, and control IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPILittle Endian HD12Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV RSV IPURSV IPD Dvdd Name GDP ZDP Supply Voltage PinsCvdd Supply voltage See NoteGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Prefix Device Family Temperature Range Default 0 C to 90 CDevice Speed Range TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingSystem-level design considerations ModePower-supply design considerations Power-supply decouplingDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset BootmodeRecommended operating conditions‡ MIN NOM MAX UnitIOH IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levelsTester Pin Electronics Output Under Test= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Input and Output Clocks PLL Mode Bypass Mode UnitTiming requirements for Clkin †‡§ See FigureGDPA-167 ParameterClkin CLKOUT3 GDPA-167 ZDPA−167 Timing requirements for ECLKIN† see Figure−200 −250Timing requirements for asynchronous memory cycles†‡§ Asynchronous Memory TimingSee −Figure AreCEx BE30 EA212 Address ED310 Read Data Setup = Strobe = Not ReadyAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdySetup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingRead Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA2113 Write EclkoutEA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Deac EclkoutRefr Eclkout CEx BE30 EA212 EA12 ED310CEx BE30 EA212 MRS value ED310 MRS EclkoutHOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Eclkout Busreq Busreq TimingReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI GDPA−167 HOST-PORT Interface TimingHstrobe Hstrobe HrdyHCS Hrdy HR/W Hhwil Hstrobe † HCS HasHas † HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXMASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Jtag TEST-PORT Timing DTCKL-TDOV Delay time, TCK low to TDO validTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTThermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice
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