Motorola TMS320C6711D warranty HR/W Hhwil Hstrobe † HCS, Has †, HR/W Hhwil Hstrobe ‡ HCS

Page 89

SPRS292 − OCTOBER 2005

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

 

 

 

1

 

1

2

 

 

2

 

 

 

 

HCNTL[1:0]

 

 

 

 

 

1

2

 

 

1

2

 

 

 

 

HR/W

 

 

 

 

 

1

2

 

 

1

2

 

 

 

 

HHWIL

 

 

 

 

 

 

3

 

 

4

3

HSTROBE†

 

 

 

 

 

 

 

 

HCS

 

 

 

 

 

 

 

15

 

 

15

 

7

9

 

16

9

HD[15:0] (output)

 

 

 

 

 

5

1st halfword

 

8

2nd halfword

5

 

 

 

17

HRDY (case 1)

 

 

 

 

 

 

 

 

 

 

6

 

8

 

5

 

 

 

17

HRDY (case 2)

 

 

 

 

 

 

 

 

 

†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 42. HPI Read Timing (HAS Not Used, Tied High)

HAS†

 

 

 

 

 

10

19

 

 

19

 

11

 

10

11

 

 

 

 

 

 

 

 

HCNTL[1:0]

 

 

 

 

 

10

11

 

10

11

 

 

 

 

 

HR/W

 

 

 

 

 

 

11

 

 

11

 

10

 

10

 

 

 

 

 

 

HHWIL

 

 

 

 

 

 

3

 

4

 

 

HSTROBE‡

 

 

 

 

 

 

18

 

 

HCS

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

15

7

 

9

16

9

 

HD[15:0] (output)

 

 

 

 

 

5

1st half-word

8

2nd half-word

17

5

 

 

HRDY (case 1)

 

 

 

 

 

 

 

8

 

17

5

HRDY (case 2)

 

 

 

 

 

†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 43. HPI Read Timing (HAS Used)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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Contents SPRS292A − October 2005 − Revised November Table of Contents Multichannel Buffered Serial Port Timing Revision HistoryPages ADDITIONS/CHANGES/DELETIONS Bottom View GDP and ZDP BGA packages bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† Description Characteristics of the C6711D Processor Device characteristicsHardware Features Internal Clock C6711DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1DA2 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryTMS320C6711D Memory Map Summary Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersHPI Registers PLL Controller RegistersGpio Registers HEX Address Range Acronym Register Name Comments Timer Timer 0 and Timer 1 RegistersMcBSP0 and McBSP1 Registers McBSP0 McBSP1Signal groups description CE2 CE3CE1 CE0GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 GpioCLKOUT2/GP2 General-Purpose Input/Output Gpio PortDevice configurations at device reset Device ConfigurationsCLKMODE0 Configuration GDP/ZDP Functional Description PINBOOTMODE‡ BIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsUsed for transfer of data, address, and control IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPILittle Endian HD12Emif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ Only one asserted during any external data accessDecoded from the two lowest bits of the internal address EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV IPD RSVRSV IPU Dvdd Name GDP ZDP Supply Voltage PinsCvdd Supply voltage See NoteGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Prefix Device Family Temperature Range Default 0 C to 90 CDevice Speed Range TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitGDPA−167, ZDPA-167 Clock SignalPLL Clock Frequency Ranges†‡ PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingSystem-level design considerations ModePower-supply design considerations Power-supply decouplingDvdd DSP Cvdd VSS GNDIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Emif big endian mode correctnessEmif Data Lines Pins Where Data Present Reset BootmodeIOH Recommended operating conditions‡MIN NOM MAX Unit IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levelsTester Pin Electronics Output Under Test= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure Input and Output Clocks PLL Mode Bypass Mode UnitTiming requirements for Clkin †‡§ See FigureClkin CLKOUT3 GDPA-167Parameter GDPA-167 ZDPA−167 Timing requirements for ECLKIN† see Figure−200 −250Timing requirements for asynchronous memory cycles†‡§ Asynchronous Memory TimingSee −Figure AreCEx BE30 EA212 Address ED310 Read Data Setup = Strobe = Not ReadyAOE/SDRAS/SSOE † AWE/SDWE/SSWE † ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold =CEx BE30 EA212 Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE†Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED310 EA2113 Write EclkoutEA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Deac EclkoutRefr Eclkout CEx BE30 EA212 EA12 ED310CEx BE30 EA212 MRS value ED310 MRS EclkoutHold Holda HOLD/HOLDA TimingTiming requirements for See Figure HOLD/HOLDA cycles† Eclkout Busreq Busreq TimingCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group† Emif Low Group† Group 2† Boot and Device PhaseClkin Eclkin Reset EXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure GDPA−167 HOST-PORT Interface TimingHstrobe Hstrobe HrdyHCS Hrdy HR/W Hhwil Hstrobe † HCS HasHas † HR/W Hhwil Hstrobe ‡ HCSHD150 input 1st half-word 2nd half-word HD150 input 1st halfword 2nd halfwordHrdy −1 ¶ Multichannel Buffered Serial Port Timing FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAXBit Bitn-1 MASTER§ Slave MINClkx FSX MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Jtag TEST-PORT Timing DTCKL-TDOV Delay time, TCK low to TDO validTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRSTThermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice
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