Motorola TMS320C6711D Interrupt sources and interrupt selector, DSP Interrupts Interrupt Selector

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

interrupt sources and interrupt selector

The C67x DSP core on the device supports 16 prioritized interrupts, which are listed in Table 20. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed in Table 20. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 21 (Interrupt Selector). Table 21 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts 4−15 is made by programming the corresponding fields (listed in Table 20) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers.

 

Table 20. DSP Interrupts

 

 

Table 21. Interrupt Selector

DSP

INTERRUPT

DEFAULT

DEFAULT

 

INTERRUPT

 

 

SELECTOR

SELECTOR

 

SELECTOR

INTERRUPT

 

INTERRUPT

INTERRUPT

 

MODULE

CONTROL

VALUE

 

VALUE

EVENT

NUMBER

EVENT

 

 

REGISTER

(BINARY)

 

(BINARY)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT_00

−

−

RESET

 

00000

DSPINT

HPI

 

 

 

 

 

 

 

 

INT_01

−

−

NMI

 

00001

TINT0

Timer 0

 

 

 

 

 

 

 

 

INT_02

−

−

Reserved

 

00010

TINT1

Timer 1

 

 

 

 

 

 

 

 

INT_03

−

−

Reserved

 

00011

SDINT

EMIF

 

 

 

 

 

 

 

 

INT_04

MUXL[4:0]

00100

GPINT4†

 

00100

GPINT4†

GPIO

INT_05

MUXL[9:5]

00101

GPINT5†

 

00101

GPINT5†

GPIO

INT_06

MUXL[14:10]

00110

GPINT6†

 

00110

GPINT6†

GPIO

INT_07

MUXL[20:16]

00111

GPINT7†

 

00111

GPINT7†

GPIO

INT_08

MUXL[25:21]

01000

EDMAINT

 

01000

EDMAINT

EDMA

 

 

 

 

 

 

 

 

INT_09

MUXL[30:26]

01001

EMUDTDMA

 

01001

EMUDTDMA

Emulation

 

 

 

 

 

 

 

 

INT_10

MUXH[4:0]

00011

SDINT

 

01010

EMURTDXRX

Emulation

 

 

 

 

 

 

 

 

INT_11

MUXH[9:5]

01010

EMURTDXRX

 

01011

EMURTDXTX

Emulation

 

 

 

 

 

 

 

 

INT_12

MUXH[14:10]

01011

EMURTDXTX

 

01100

XINT0

McBSP0

 

 

 

 

 

 

 

 

INT_13

MUXH[20:16]

00000

DSPINT

 

01101

RINT0

McBSP0

 

 

 

 

 

 

 

 

INT_14

MUXH[25:21]

00001

TINT0

 

01110

XINT1

McBSP1

 

 

 

 

 

 

 

 

INT_15

MUXH[30:26]

00010

TINT1

 

01111

RINT1

McBSP1

 

 

 

 

 

 

 

 

 

 

 

 

 

10000

GPINT0

GPIO

 

 

 

 

 

 

 

 

†Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins GP[4](EXT_INT4), GP[5](EXT_INT5), GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

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Contents SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal ClockDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description ST2 ST1DA1 DA2TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache RegistersHEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM†Quick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersHPI Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description CE0 CE3CE2 CE1General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2Device configurations at device reset Device ConfigurationsBOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and InterruptsHD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little EndianDecoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0RSV IPU RSVRSV IPD Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd CvddGND Description Name GDP ZDP Supply Voltage PinsGround Pins VSSVSS PIN Signal TYPE† Description Name GDP ZDP Ground PinsVSS GND Description Name GDP ZDP Ground PinsSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed RangeDocumentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID PwrdCPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt SelectorEdma Channels Edma module and Edma selectorEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or DisabledPLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterMode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsDSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations DvddIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset BootmodeMIN NOM MAX Unit Recommended operating conditions‡IOH IOZ Parameter Test Conditions MIN TYP MAX UnitOutput Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§Parameter GDPA-167Clkin CLKOUT3 −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −FigureAWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE †CEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory TimingARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram TimingEA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE†CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr EclkoutCEx BE30 EA212 MRS value ED310 MRS EclkoutTiming requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Eclkout Busreq Busreq TimingTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 HstrobeHCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has †Hrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resyncClkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDPQty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak TempSeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice
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