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| SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 |
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| Terminal Functions (Continued) |
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| PIN |
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SIGNAL | NO. | TYPE† | IPD/ |
| DESCRIPTION |
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NAME | GDP/ | IPU‡ |
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| ZDP |
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| EMIF − DATA (CONTINUED) ¶ |
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ED18 | Y3 |
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ED17 | W4 |
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ED16 | V4 |
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ED15 | T19 |
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ED14 | T20 |
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ED13 | T18 |
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ED12 | R20 |
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ED11 | R19 |
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ED10 | P20 |
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ED9 | P18 | I/O/Z | IPU |
| External data |
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ED8 | N20 |
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ED7 | N19 |
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ED6 | N18 |
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ED5 | M20 |
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ED4 | M19 |
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ED3 | L19 |
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ED2 | L18 |
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ED1 | K19 |
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ED0 | K18 |
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| TIMER 1 |
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TOUT1 | F1 | O | IPD |
| Timer 1 or |
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TINP1 | F2 | I | IPD |
| Timer 1 or |
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| TIMER 0 |
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TOUT0 | G1 | O | IPD |
| Timer 0 or |
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TINP0 | G2 | I | IPD |
| Timer 0 or |
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| MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) |
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| External clock source (as opposed to internal) |
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| On the device, this pin does not have an internal pulldown (IPD). For proper device opera- |
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CLKS1 | E1 | I | IPD |
| tion, the CLKS1 pin should either be driven externally at all times or be pulled up with a |
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| resistor to a valid logic level. Because it is common for some ICs to |
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| times, a |
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| pin. |
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CLKR1 | M1 | I/O/Z | IPD |
| Receive clock |
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CLKX1 | L3 | I/O/Z | IPD |
| Transmit clock |
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†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
¶To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 | 29 |