SMSC COM20020 manual MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface

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XTAL1

COM20020

 

 

 

XTAL2

 

 

 

AD0-AD7

AD0-AD2, D3-D7

 

 

ALE

A2/BALE

RXIN

 

A15

nCS

 

 

 

RESET

nRESET IN

nTXEN

75176B or

Equiv.

 

 

nPULSE1

 

nRD

nRD/nDS

nPULSE2

 

nWR

nWR/DIR

GND

 

nINT1

nINTR

 

 

 

 

 

 

Differential Driver

 

A0/nMUX

 

Configuration

 

 

 

 

XTAL1

XTAL2

*Media Interface

 

may be replaced

 

 

 

8051

 

 

with Figure A, B or C.

27 pF

27 pF

 

 

 

FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE

RXIN

TXEN

nPULSE1

nPULSE2

GND

+5V

100 Ohm

+5V

2

6 Receiver

RXIN

HFD3212-002

7

Transmitter

3 HFE4211-014

nPULSE1

+5V

2

6

7

2 Fiber Interface

(ST Connectors)

BACKPLANE CONFIGURATION

NOTE: COM20020 must be in backplane mode

FIGURE A

FIGURE B

13

Image 13
Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsTransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Protocol Description Network ReconfigurationNetwork Protocol Data RatesBroadcast Messages Extended Timeout FunctionResponse Time Idle Time Reconfiguration Time Line Protocol Invitations To TransmitAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Attenuation Functional DescriptionNominal Cable Type Impedance AT 5MHZRead Register Summary Write Interrupt Mask Register IMR Internal RegistersData Register Tentative ID RegisterCommand Register Diagnostic Status RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Access Speed Sequential Access MemoryInternal RAM Software InterfaceTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator DC Electrical Characteristics Maximum Guaranteed RatingsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp