SMSC COM20020 manual Address Pointer High Register, Address Pointer Low Register

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Table 7 - Address Pointer High Register

BIT	BIT NAME	SYMBOL	DESCRIPTION

7	Read Data	RDDATA	This bit tells the COM20020 whether the following access
			will be a read or write. A logic "1" prepares the device for
			a read, a logic "0" prepares it for a write.

6	Auto Increment	AUTOINC	This bit controls whether the address pointer will
			increment automatically. A logic "1" on this bit allows
			automatic increment of the pointer after each access,
			while a logic "0" disables this function. Please refer to
			the Sequential Access Memory section for further detail.

5-3	(reserved)		These bits are undefined.

2-0	Address 10-8	A10-A8	These bits hold the upper three address bits which
			provide addresses to RAM.

Table 8 - Address Pointer Low Register

BIT	BIT NAME	SYMBOL	DESCRIPTION

7-0	Address 7-0	A7-A0	These bits hold the lower 8 address bits which provide
			the addresses to RAM.

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALETransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Reconfiguration Protocol DescriptionNetwork Protocol Data RatesBroadcast Messages Extended Timeout FunctionResponse Time Reconfiguration Time Idle TimeLine Protocol Invitations To TransmitAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Functional Description AttenuationNominal Cable Type Impedance AT 5MHZRead Register Summary Write Internal Registers Interrupt Mask Register IMRData Register Tentative ID RegisterDiagnostic Status Register Command RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Sequential Access Memory Access SpeedInternal RAM Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Maximum Guaranteed Ratings DC Electrical CharacteristicsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp