SMSC COM20020 manual Command Register, Data Command Description

Page 27

 

 

Table 6 - Command Register

DATA

COMMAND

 

DESCRIPTION

 

 

 

 

0000 0000

Clear

 

This command is used only in the Command Chaining operation. Please

 

Transmit

 

refer to the Command Chaining section for definition of this command.

 

Interrupt

 

 

 

 

 

 

0000 0001

Disable

 

This command will cancel any pending transmit command (transmission

 

Transmitter

 

that has not yet started) and will set the TA (Transmitter Available) status

 

 

 

bit to logic "1" when the COM20020 next receives the token.

 

 

 

 

0000 0010

Disable

 

This command will cancel any pending receive command. If the

 

Receiver

 

COM20020 is not yet receiving a packet, the RI (Receiver Inhibited) bit will

 

 

 

be set to logic "1" the next time the token is received. If packet reception is

 

 

 

already underway, reception will run to its normal conclusion.

 

 

 

 

b0fn n100

Enable

 

This command allows the COM20020 to receive data packets into RAM

 

Receive to

 

buffer page fnn and resets the RI status bit to logic "0". The values placed

 

Page fnn

 

in the "nn" bits indicate the page that the data will be received into (page 0,

 

 

 

1, 2, or 3). If the value of "f" is a logic "1", an offset of 256 bytes will be

 

 

 

added to that page specified in "nn", allowing a finer resolution of the

 

 

 

buffer. Refer to the Selecting RAM Page Size section for further detail. If

 

 

 

the value of "b" is logic "1", the device will also receive broadcasts

 

 

 

(transmissions to ID zero). The RI status bit is set to logic "1" upon

 

 

 

successful reception of a message.

 

 

 

 

00fn n011

Enable

 

This command prepares the COM20020 to begin a transmit sequence

 

Transmit from

 

from RAM buffer page fnn the next time it receives the token. The values

 

Page fnn

 

of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3). If "f" is

 

 

 

logic "1", an offset of 256 bytes is the start of the page specified in "nn",

 

 

 

allowing a finer resolution of the buffer. Refer to the Selecting RAM Page

 

 

 

Size section for further detail. When this command is loaded, the TA and

 

 

 

TMA bits are reset to logic "0". The TA bit is set to logic "1" upon

 

 

 

completion of the transmit sequence. The TMA bit will have been set by

 

 

 

this time if the device has received an ACK from the destination node. The

 

 

 

ACK is strictly hardware level, sent by the receiving node before its

 

 

 

microcontroller is even aware of message reception. Refer to Figure 1 for

 

 

 

details of the transmit sequence and its relation to the TA and TMA status

 

 

 

bits.

 

 

 

 

0000 c101

Define

 

This command defines the maximum length of packets that may be

 

Configuration

 

handled by the device. If "c" is a logic "1", the device handles both long

 

 

 

and short packets. If "c" is a logic "0", the device handles only short

 

 

 

packets.

 

 

 

 

000r p110

Clear Flags

 

This command resets certain status bits of the COM20020. A logic "1" on

 

 

 

"p" resets the POR status bit and the EXCNAK Diagnostic status bit. A

 

 

 

logic "1" on "r" resets the RECON status bit.

 

 

 

 

0000 1000

Clear

 

This command is used only in the Command Chaining operation. Please

 

Receive

 

refer to the Command Chaining section for definition of this command.

 

Interrupt

 

 

 

 

 

 

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Data Rates Network ReconfigurationProtocol Description Network ProtocolExtended Timeout Function Broadcast MessagesResponse Time Invitations To Transmit Reconfiguration TimeIdle Time Line ProtocolData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Cable Type Impedance AT 5MHZ Functional DescriptionAttenuation NominalRead Register Summary Write Tentative ID Register Internal RegistersInterrupt Mask Register IMR Data RegisterStatus Register Diagnostic Status RegisterCommand Register Next ID Register Configuration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Software Interface Sequential Access MemoryAccess Speed Internal RAMTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator Operational Description Maximum Guaranteed RatingsDC Electrical Characteristics Parameter Symbol MIN TYP MAX Unit CommentXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp
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