SMSC COM20020 manual Initialization Sequence, Improved Diagnostics

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INITIALIZATION SEQUENCE

Bus Determination

Writing to and reading from an odd address location from the COM20020's address space causes the COM20020 to determine the appropriate bus interface. When the COM20020 is powered on the internal registers may be written to. Since writing a non-zero value to the Node ID Register wakes up the core, the Setup Register should be written to before the Node ID Register. Until a non-zero value is placed into the NID Register, no microcode is executed, no tokens are passed by this node, and no reconfigurations are generated by this node.

Once a non-zero value is placed in the register, the core wakes up, but the node will not attempt to join the network until the TX Enable bit of the Configuration Register is set.

Before setting the TX Enable bit, the software may make some determinations. The software may first observe the Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health of the receiver and the network.

Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable bit should still be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the Duplicate ID bit of the Diagnostic Status Register is set after a maximum of 840mS (or 1680mS if the ET1 and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the COM20020 compares the value in the Node ID Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared. The user may then attempt a new ID value, wait 840mS before checking the Duplicate ID bit, and repeat the process until a unique Node ID is found. At this point, the TX Enable bit may be set to allow the

node to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the MYRECON bit of the Diagnostic Status Register.

The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the COM20020 has joined the network. Once a value is placed in the Tentative ID Register, the COM20020 looks for a response to a token whose DID matches the Tentative ID Register. The software can record this information and continue placing Tentative ID values into the register to continue building the network map. A complete network map is only valid until nodes are added to or deleted from the network. Note that a node cannot detect the existence of the next logical node on the network when using the Tentative ID. To determine the next logical node, the software should read the Next ID Register.

IMPROVED DIAGNOSTICS

The COM20020 allows the user to better manage the operation of the network through the use of the internal Diagnostic Status Register.

A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired, causing a

reconfiguration by this node. After the Reconfiguration (RECON) bit of the Status Register interrupts the microcontroller, the interrupt service routine will typically read the MYRECON bit of the Diagnostic Status

Register. Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be disabled so that the entire network is not held down while the node is being evaluated.

The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALETransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Reconfiguration Protocol DescriptionNetwork Protocol Data RatesBroadcast Messages Extended Timeout FunctionResponse Time Reconfiguration Time Idle TimeLine Protocol Invitations To TransmitAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Functional Description AttenuationNominal Cable Type Impedance AT 5MHZRead Register Summary Write Internal Registers Interrupt Mask Register IMRData Register Tentative ID RegisterDiagnostic Status Register Command RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Sequential Access Memory Access SpeedInternal RAM Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Maximum Guaranteed Ratings DC Electrical CharacteristicsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp
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