SMSC COM20020 Normal Mode Transmit or Receive Timing, These signals are to and from the hybrid

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nTXEN

t4

nPULSE1

nPULSE2

	t2	t5
	t1
		LAST BIT
	t3	(400 nS BIT TIME)
	t3	t2
	t1	t2
	t1

RXIN

t6

t7

	Parameter	min	typ		max	units
t1	nPULSE1, nPULSE2 Pulse Width		100	*		nS
t2	nPULSE1, nPULSE2 Period		400	*		nS
t3	nPULSE1, nPULSE2 Overlap	-10	0		+10	nS
t4	nTXEN Low to nPULSE1 Low**	850			950	nS
t5	Beginning of Last Bit Time to nTXEN High**	250			350	nS
t6	RXIN Pulse Width	10	100*			nS
t7	RXIN Period		400	*		nS

*t1 = 2 x (crystal period) for clock frequencies other than 20 MHz.

*t2,t7 = 8 x (crystal period) for clock frequencies other than 20 MHz. This period applies to data of two consecutive one's.

**t4: For clock frequencies other than 20 MHz, t4 = 18 x (crystal period)+ 50 nsec.

**t5: For clock frequencies other than 20 MHz, t5 = 6 x (crystal period)+ 50 nsec.

FIGURE 14 - NORMAL MODE TRANSMIT OR RECEIVE TIMING

(These signals are to and from the hybrid)

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Protocol Network ReconfigurationProtocol Description Data RatesExtended Timeout Function Broadcast MessagesResponse Time Line Protocol Reconfiguration TimeIdle Time Invitations To TransmitData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Nominal Functional DescriptionAttenuation Cable Type Impedance AT 5MHZRead Register Summary Write Data Register Internal RegistersInterrupt Mask Register IMR Tentative ID RegisterNext ID Register Diagnostic Status RegisterCommand Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Internal RAM Sequential Access MemoryAccess Speed Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Parameter Symbol MIN TYP MAX Unit Comment Maximum Guaranteed RatingsDC Electrical Characteristics Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp