INTERNAL RAM
The integration of the 2K x 8 RAM in the COM20020 represents significant real estate savings. The most obvious benefit is the
Sequential Access Memory
The internal RAM is accessed via a pointer- based scheme. Rather than interfering with system memory, the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is channeled to and from the microcontroller via the
microcontroller. This process is
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continued until the entire packet is read out of RAM. Refer to Figure 7 for an illustration of the Sequential Access operation. When switching between reads and writes, the pointer must first be written with the starting address. At least one cycle time should separate the pointer being loaded and the first read (see timing parameters).
Access Speed
The COM20020 is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to memory.
For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the Setup Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by two, the duty cycle of the input clock may be relaxed.
SOFTWARE INTERFACE
The microcontroller interfaces to the COM20020 via software by accessing the various registers. These actions are described in the Internal Registers section. The software flow for accessing the data buffer is based on the
Sequential Access scheme. The basic sequence is as follows:
∙Disable Interrupts
∙Write to Pointer Register High (specifying
∙Write to Pointer Register Low (this loads the address.)
∙Enable Interrupts
∙Read or write the Data Register (repeat as many times as necessary to empty or fill the buffer).