SMSC COM20020 manual BIT BIT Name Symbol Description, Dupid

Page 26

Table 5 - Diagnostic Status Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

 

 

 

 

 

7

My Reconfiguration

MY-

This bit, if high, indicates that a past reconfiguration was caused by this

 

 

RECON

node. It is set when the Lost Token Timer times out, and should be typically

 

 

 

read following an interrupt caused by RECON. Refer to the Improved

 

 

 

Diagnostics section for further detail.

 

 

 

 

 

6

Duplicate ID

DUPID

This bit, if high, indicates that the value in the Node ID Register matches

 

 

 

both Destination ID characters of the token and a response to this token has

 

 

 

occurred. Trailing zero's are also verified. A logic "1" on this bit indicates a

 

 

 

duplicate Node ID, thus the user should write a new value into the Node ID

 

 

 

Register. This bit is only useful for duplicate ID detection when the device is

 

 

 

off line, that is, when the transmitter is disabled. When the device is on line

 

 

 

this bit will be set every time the device gets the token. This bit is reset

 

 

 

automatically upon reading the Diagnostic Status Register. Refer to the

 

 

 

Improved Diagnostics section for further detail.

 

 

 

 

 

5

Receive

RCVACT

This bit, if high, indicates that data activity (logic "1") was detected on the

 

Activity

 

RXIN pin of the device. Refer to the Improved

Diagnostics section for

 

 

 

further detail.

 

 

 

 

 

4

Token Seen

TOKEN

This bit, if high, indicates that a token has been seen on the network, sent by

 

 

 

a node other than this one. Refer to the Improved Diagnostic section for

 

 

 

further detail.

 

 

 

 

 

3

Excessive NAK

EXCNAK

This bit, if high, indicates that either 128 or 4 Negative Acknowledgements

 

 

 

have occurred in response to the Free Buffer Enquiry. This bit is cleared

 

 

 

upon the "POR Clear Flags" command. Reading the Diagnostic Status

 

 

 

Register does not clear this bit. This bit, when set, will cause an interrupt if

 

 

 

the corresponding bit in the IMR is also set. Refer to the Improved

 

 

 

Diagnostics section for further detail.

 

 

 

 

 

2

Tentative ID

TENTID

This bit, if high, indicates that a response to a token whose DID matches the

 

 

 

value in the Tentative ID Register has occurred. The second DID and the

 

 

 

trailing zero's are not checked. Since each node sees every token passed

 

 

 

around the network, this feature can be used with the device on-line in order

 

 

 

to build and update a network map. Refer to the Improved Diagnostics

 

 

 

section for further detail.

 

 

 

 

 

1

New Next ID

NEW

This bit, if high, indicates that the Next ID Register has been updated and

 

 

NXTID

that a node has either joined or left the network.

Reading the Diagnostic

 

 

 

Status Register does not clear this bit. This bit, when set, will cause an

 

 

 

interrupt if the corresponding bit in the IMR is also set. The bit is cleared by

 

 

 

reading the Next ID Register.

 

 

 

 

 

 

1,0

(Reserved)

 

These bits are undefined.

 

 

 

 

 

 

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEMiscellaneous DIP PIN Plcc PIN Name Symbol DescriptionTransmission Media Interface Instead, it must be connected to XTAL1 with COM20020 Operation Network Protocol Network ReconfigurationProtocol Description Data RatesResponse Time Extended Timeout FunctionBroadcast Messages Line Protocol Reconfiguration TimeIdle Time Invitations To TransmitNegative Acknowledgements Data PacketsAcknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Nominal Functional DescriptionAttenuation Cable Type Impedance AT 5MHZRead Register Summary Write Data Register Internal RegistersInterrupt Mask Register IMR Tentative ID RegisterNext ID Register Diagnostic Status RegisterCommand Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Internal RAM Sequential Access MemoryAccess Speed Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Parameter Symbol MIN TYP MAX Unit Comment Maximum Guaranteed RatingsDC Electrical Characteristics Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp
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