SMSC COM20020 manual Read Register Summary

Page 20

Table 2 - Read Register Summary

					READ
	REGISTER	MSB							LSB	ADDRESS

	STATUS	RI	X	X	POR	TEST	RECON	TMA	TA	00

	DIAG.	MY-						NEW		01
	STATUS	RECON	DUPID RCVACT TOKEN EXCNAK TENTID NEXTID						X	01

	ADDRESS	RDDATA	AUTO-	X	X	X	A10	A9	A8	02
	PTR HIGH	RDDATA	INC	X	X	X	A10	A9	A8	02
	PTR HIGH		INC

	ADDRESS	A7	A6	A5	A4	A3	A2	A1	A0	03
	PTR LOW	A7	A6	A5	A4	A3	A2	A1	A0	03
	PTR LOW

	DATA	D7	D6	D5	D4	D3	D2	D1	D0	04

	RESERVED	X	X	X	X	X	X	X	X	05

	CONFIG-	RESET	CCHEN	TXEN	ET1	ET2	BACK-	SUB-	SUB-	06
	URATION	RESET	CCHEN	TXEN	ET1	ET2	PLANE	AD1	AD0	06
	URATION						PLANE	AD1	AD0

	TENTID	TID7	TID6	TID5	TID4	TID3	TID2	TID1	TID0
	NODEID
	NODEID	NID7	NID6	NID5	NID4	NID3	NID2	NID1	NID0	07

	SETUP	P1MODE	FOUR	ET3	RCV_	CKP3	CKP2	CKP1	SLOW
			FOUR		RCV_				SLOW
			NAKS		ALL				ARB
			NAKS		ALL				ARB

NEXT ID

NXTID7 NXTID6 NXTID5 NXTID4 NXTID3 NXTID2 NXTID1 NXTID0

20

Image 20

Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEMiscellaneous DIP PIN Plcc PIN Name Symbol DescriptionTransmission Media Interface Instead, it must be connected to XTAL1 with COM20020 Operation Network Reconfiguration Protocol DescriptionNetwork Protocol Data RatesResponse Time Extended Timeout FunctionBroadcast Messages Reconfiguration Time Idle TimeLine Protocol Invitations To TransmitNegative Acknowledgements Data PacketsAcknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Functional Description AttenuationNominal Cable Type Impedance AT 5MHZRead Register Summary Write Internal Registers Interrupt Mask Register IMRData Register Tentative ID RegisterDiagnostic Status Register Command RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Sequential Access Memory Access SpeedInternal RAM Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Maximum Guaranteed Ratings DC Electrical CharacteristicsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp