SMSC COM20020 manual Internal Block Diagram

Page 18

A0/nMUX
A1
A2/BALE	ADDRESS
	ADDRESS
	DECODING
	CIRCUITRY

AD0-AD2,

D3-D7

2K x 8

RAM

ADDITIONAL

REGISTERS

nINTR	STATUS/
nINTR	COMMAND			nPULSE1
	REGISTER	MICRO-	TX/RX	nPULSE2
		SEQUENCER	TX/RX	nTXEN
		SEQUENCER	LOGIC
		AND	LOGIC
		AND		RXIN
		WORKING		RXIN
		WORKING
nRESET IN	RESET	REGISTERS
nRESET IN	LOGIC
	LOGIC
			OSCILLATOR	XTAL1
			OSCILLATOR	XTAL2
				XTAL2
nRD/nDS
nWR/DIR	BUS
	BUS
nCS	ARBITRATION
	CIRCUITRY RECONFIGURATION		NODE ID
		TIMER	LOGIC

FIGURE 6 - INTERNAL BLOCK DIAGRAM

18

Image 18

Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Protocol Network ReconfigurationProtocol Description Data RatesExtended Timeout Function Broadcast MessagesResponse Time Line Protocol Reconfiguration TimeIdle Time Invitations To TransmitData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Nominal Functional DescriptionAttenuation Cable Type Impedance AT 5MHZRead Register Summary Write Data Register Internal RegistersInterrupt Mask Register IMR Tentative ID RegisterNext ID Register Diagnostic Status RegisterCommand Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Internal RAM Sequential Access MemoryAccess Speed Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Parameter Symbol MIN TYP MAX Unit Comment Maximum Guaranteed RatingsDC Electrical Characteristics Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp