| VALID |
| |
|
|
| |
| t1 |
| t2 |
nCS |
|
|
|
|
|
| t4 |
DIR | t3 |
|
|
| t5 | t6 | t7 |
nDS |
|
| |
|
| Note 2 | |
|
|
| |
|
| t8 | t6** |
|
|
| t9 |
| VALID DATA |
|
| Parameter | min | max | units |
t1 | Address Setup to nDS Active | 15 |
| nS |
t2 | Address Hold from nDS Inactive | 10 |
| nS |
t3 | nCS Setup to nDS Active | 5 |
| nS |
t4 | nCS Hold from nDS Inactive | 0 |
| nS |
t5 | DIR Setup to nDS Active | 10 |
| nS |
t6 | Cycle Time (nDS Low to Next Time Low)** | 4T* |
| nS |
t7 | DIR Hold from nDS Inactive | 10 |
| nS |
t8 | Valid Data Setup to nDS High | 30** |
| nS |
t9 | Data Hold from nDS High | 10 |
| nS |
|
|
|
|
|
*T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0, T is twice XTAL1 period if SLOW ARB = 1
**nCS may become active after control becomes active, but the data setup time will now be 30 nS measured from the later of nCS falling or Valid Data available.
Note 1:
Note 2:
The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering
Any cycle occurring after a write to the Address Pointer Low Register requires a minimum of 4T from the trailing edge of nDS to the leading edge of the next nDS.
FIGURE 13A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
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