SMSC COM20020 manual Transmit Command Chaining

Page 37

M S B

T R I

T R I

R I

TA

P O R

T E S T

R E C O N

T M A

T M A

L S B

TTA

TTA

 

 

FIGURE 9 - COMMAND CHAINING STATUS REGISTER QUEUE

 

 

 

 

 

 

 

 

 

 

 

∙ Up to two outstanding transmit interrupts

COMMAND CHAINING

 

 

 

 

 

and two outstanding receive interrupts are

 

 

 

 

 

 

 

 

 

stored by the device, along with their

The Command Chaining operation allows

 

respective status bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

consecutive transmissions

and

receptions to

∙ The Interrupt Mask bits act on TTA (Rising

occur without host microcontroller intervention.

 

Transition on

Transmitter

Available) for

Through

the use of a dual two-level

FIFO,

 

 

transmit

operations

and

TRI

(Rising

commands to be transmitted and received, as

 

 

Transition of Receiver Inhibited) for receive

well as the status bits, are pipelined.

 

 

 

 

 

 

operations. TTA is set upon completion of

 

 

 

 

 

 

 

 

 

In

order

for the COM20020 to

be

compatible

 

a packet transmission only. TRI is set upon

 

completion of

a

packet reception

only.

with previous SMSC ARCNET

device

drivers,

 

 

Typically there is no need to mask the TTA

the device defaults to the non-chaining mode.

 

 

and TRI bits after clearing the interrupt.

In order to take advantage of the Command

 

 

 

 

 

 

 

 

 

 

Chaining

operation,

the Command Chaining

∙

The traditional

TA and RI

bits

are still

Mode must be enabled via a logic "1" on bit 6 of

 

available to reflect the present status of the

the Configuration Register.

 

 

 

 

 

 

 

 

 

 

device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In Command Chaining, the Status Register

Transmit Command Chaining

 

 

 

appears as in Figure 9.

 

 

 

 

 

 

 

The following is a list of Command Chaining

When the processor issues the first "Enable

guidelines for the software programmer. Further

Transmit to Page fnn" command, the

detail can be found in the Transmit Command

COM20020 responds in the usual manner by

Chaining and Receive Command Chaining

resetting the TA and TMA bits to prepare for the

sections.

 

 

 

 

 

 

transmission from the specified page.

The TA

 

 

 

 

 

 

 

 

bit can be used to see if there is currently a

∙

The device is designed such that the interrupt

transmission

pending,

but

the TA bit

is

really

meant to be

used

in

the

non-chaining

mode

 

service

routine

latency

does

not

affect

 

only.

The

TTA

bits provide

the

relevant

 

performance.

 

 

 

 

 

 

 

 

 

 

 

information for the device in the Command

 

 

 

 

 

 

 

 

∙

Up to two outstanding transmissions and two

Chaining mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

outstanding receptions can be pending at any given time. The commands may be given in any order.

37

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsTransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Protocol Description Network ReconfigurationNetwork Protocol Data RatesBroadcast Messages Extended Timeout FunctionResponse Time Idle Time Reconfiguration TimeLine Protocol Invitations To TransmitAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Attenuation Functional DescriptionNominal Cable Type Impedance AT 5MHZRead Register Summary Write Interrupt Mask Register IMR Internal RegistersData Register Tentative ID RegisterCommand Register Diagnostic Status RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Access Speed Sequential Access MemoryInternal RAM Software InterfaceTransmit Sequence Selecting RAM Page Size RAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator DC Electrical Characteristics Maximum Guaranteed RatingsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp
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