SMSC COM20020 manual Standard Microsystems Corp

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STANDARD MICROSYSTEMS CORP.	Circuit diagrams utilizing SMSC products are included as a means of illustrating
	typical applications; consequently complete information sufficient for
	construction purposes is not necessarily given. The information has been
	carefully checked and is believed to be entirely reliable. However, no
	responsibility is assumed for inaccuracies. Furthermore, such information does
	not convey to the purchaser of the semiconductor devices described any
	licenses under the patent rights of SMSC or others. SMSC reserves the right to
	make changes at any time in order to improve design and supply the best
	product possible. SMSC products are not designed, intended, authorized or
	warranted for use in any life support or other application where product failure
	could cause or contribute to personal injury or severe property damage. Any
	and all such uses without prior written approval of an Officer of SMSC and
	further testing and/or modification will be fully at the risk of the customer.
	COM20020 Rev. 5/29/96

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Reconfiguration Protocol DescriptionNetwork Protocol Data RatesExtended Timeout Function Broadcast MessagesResponse Time Reconfiguration Time Idle TimeLine Protocol Invitations To TransmitData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Functional Description AttenuationNominal Cable Type Impedance AT 5MHZRead Register Summary Write Internal Registers Interrupt Mask Register IMRData Register Tentative ID RegisterDiagnostic Status Register Command RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Sequential Access Memory Access SpeedInternal RAM Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Maximum Guaranteed Ratings DC Electrical CharacteristicsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp