SMSC COM20020 manual Table of Contents

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TABLE OF CONTENTS
FEATURES	1
GENERAL DESCRIPTION	1
PIN CONFIGURATION	3
DESCRIPTION OF PIN FUNCTIONS	4
PROTOCOL DESCRIPTION	8
NETWORK PROTOCOL	8
DATA RATES	8
NETWORK RECONFIGURATION	8
BROADCAST MESSAGES	9
EXTENDED TIMEOUT FUNCTION	9
LINE PROTOCOL	10
SYSTEM DESCRIPTION	12
MICROCONTROLLER INTERFACE	12
TRANSMISSION MEDIA INTERFACE	15
FUNCTIONAL DESCRIPTION	19
MICROSEQUENCER	19
INTERNAL REGISTERS	22
INTERNAL RAM	32
COMMAND CHAINING	37
INITIALIZATION SEQUENCE	40
IMPROVED DIAGNOSTICS	40
OPERATIONAL DESCRIPTION	43
MAXIMUM GUARANTEED RATINGS*	43
DC ELECTRICAL CHARACTERISTICS	43
TIMING DIAGRAMS	46
COM20020 ERRATA SHEET	59

For more details on the ARCNET protocol engine and traditional dipulse signalling schemes, please refer to the ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the ARCNET Designer's Handbook, available from Datapoint Corporation.

For more detailed information on cabling options including RS485, transformer-coupled RS- 485 and Fiber Optic interfaces, please refer to the following technical note which is available from Standard Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020 ULANC.

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEMiscellaneous DIP PIN Plcc PIN Name Symbol DescriptionTransmission Media Interface Instead, it must be connected to XTAL1 with COM20020 Operation Network Protocol Network ReconfigurationProtocol Description Data RatesResponse Time Extended Timeout FunctionBroadcast Messages Line Protocol Reconfiguration TimeIdle Time Invitations To TransmitNegative Acknowledgements Data PacketsAcknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Nominal Functional DescriptionAttenuation Cable Type Impedance AT 5MHZRead Register Summary Write Data Register Internal RegistersInterrupt Mask Register IMR Tentative ID RegisterNext ID Register Diagnostic Status RegisterCommand Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Internal RAM Sequential Access MemoryAccess Speed Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Parameter Symbol MIN TYP MAX Unit Comment Maximum Guaranteed RatingsDC Electrical Characteristics Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp