SMSC COM20020 manual Figure C

Page 14

XTAL1

XTAL2

D0-D7

A0

A1

A2

A7

nRES

nIOS R/nW nIRQ1

6801

COM20020
D0-D7
A0/nMUX		RXIN
A1		RXIN
A1
A2/BALE			75176B or
nCS			75176B or
nCS		TXEN	Equiv.
nRESET IN		nPULSE1
nRESET IN		nPULSE2
		nPULSE2
nRD/nDS		GND
nRD/nDS
nWR/nDIR			Differential Driver
nINTR			Differential Driver
nINTR			Configuration
XTAL1	XTAL2		* Media Interface
XTAL1			may be replaced
			may be replaced

with Figure A, B or C.

27 pF

20MHz

27 pF

XTAL

FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE

		+5V
	HYC9068 or	10	+	0.47
	HYC9088	10	+	0.47
	HYC9088	uF		uF
		uF		uF
RXIN	RXIN	6
RXIN	RXIN
		12
nTXEN	N/C	11		0.01 uF
		11	5.6K

nPULSE1	nPULSE1			1KV
nPULSE1	nPULSE1		1/2W	1KV
			1/2W
nPULSE2	nPULSE2		5.6K
GND	17, 19,		1/2W
	17, 19,
	4, 13, 14
	4, 13, 14
		3
	0.47		Traditional Hybrid
	0.47	-5V	Configuration
	uF	-5V	Configuration
		+ 10
		uF

FIGURE C

14

Image 14

Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEMiscellaneous DIP PIN Plcc PIN Name Symbol DescriptionTransmission Media Interface Instead, it must be connected to XTAL1 with COM20020 Operation Network Protocol Network ReconfigurationProtocol Description Data RatesResponse Time Extended Timeout FunctionBroadcast Messages Line Protocol Reconfiguration TimeIdle Time Invitations To TransmitNegative Acknowledgements Data PacketsAcknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Nominal Functional DescriptionAttenuation Cable Type Impedance AT 5MHZRead Register Summary Write Data Register Internal RegistersInterrupt Mask Register IMR Tentative ID RegisterNext ID Register Diagnostic Status RegisterCommand Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Internal RAM Sequential Access MemoryAccess Speed Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Parameter Symbol MIN TYP MAX Unit Comment Maximum Guaranteed RatingsDC Electrical Characteristics Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp