SMSC COM20020 manual Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle

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AD0-AD2, D3-D7

nCS

ALE

nDS

DIR

VALID

t1 t2,

t4

t3

t5

t9

VALID DATA

t7

t6

Note 2 t8**

t8

t10

 

Parameter

min

max

units

 

 

 

 

 

t1

Address Setup to ALE Low

30

 

nS

t2

Address Hold from ALE Low

10

 

nS

t3

nCS Setup to ALE Low

10

 

nS

t4

nCS Hold from ALE Low

20

 

nS

t5

ALE Low to nDS Low

15

 

nS

t6

Valid Data Setup to nDS High

30

 

nS

t7

Data Hold from nDS High

10

 

nS

t8

Cycle Time (nDS Low to Next Time Low)**

4T*

 

nS

t9

DIR Setup to nDS Active

10

 

nS

t10

DIR Hold from nDS Inactive

10

 

nS

 

 

 

 

 

*T is the Arbitration Clock Period.

T is identical to XTAL1 if SLOW ARB = 0, T is twice XTAL1 period if SLOW ARB = 1

Note 1: The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020 cycles.

**Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4T from the trailing edge of nDS to the leading edge of the next nDS.

FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE

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Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Reconfiguration Protocol DescriptionNetwork Protocol Data RatesExtended Timeout Function Broadcast MessagesResponse Time Reconfiguration Time Idle TimeLine Protocol Invitations To TransmitData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Functional Description AttenuationNominal Cable Type Impedance AT 5MHZRead Register Summary Write Internal Registers Interrupt Mask Register IMRData Register Tentative ID RegisterDiagnostic Status Register Command RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Sequential Access Memory Access SpeedInternal RAM Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Maximum Guaranteed Ratings DC Electrical CharacteristicsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp