SMSC COM20020 manual NTXEN NPULSE1

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nTXEN

t1

nPULSE1

nPULSE2 (Internal Clk)

RXIN

t9

t4

t10

t3

t2

t8

LAST BIT (400 nS BIT TIME)

t5 t6

t7

t11

	Parameter	min	typ	max	units

t1	nPULSE2 High to nTXEN Low	0		50	nS
t2	nPULSE1 Pulse Width		200*		nS
t3	nPULSE1 Period	-25	400*		nS
t4	nPULSE2 Low to nPULSE1 Low	-25	100*	25	nS
t5	nPULSE2 High Time		100*		nS
t6	nPULSE2 Low Time		100*		nS
t7	nPULSE2 Period		200*	50	nS
t8	nPULSE2 High to nTXEN High	0		50	nS
t9	(First rising edge on nPULSE2 after Last Bit Time)	650		750	nS
t9	nTXEN Low to first nPULSE1 Low**	650		750	nS
t10	RXIN Pulse Width	10	200*		nS
t11	RXIN Period		400*		nS

*t5,t6 = 2 x (crystal period) for clock frequencies other than 20 MHz.

*t2,t7,t10 = 4 x (crystal period) for clock frequencies other than 20 MHz.

*t3,t11 = 8 x (crystal period) for clock frequencies other than 20 MHz.

This period applies to data of two consecutive one's.

** t9: For clock frequencies other than 20 MHz, t9 = 14 x (clock period) + 50 nsec.

FIGURE 15 - BACKPLANE MODE TRANSMIT OR RECEIVE TIMING (These signals are to and from the differential driver or the cable)

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsTransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Data Rates Network ReconfigurationProtocol Description Network ProtocolBroadcast Messages Extended Timeout FunctionResponse Time Invitations To Transmit Reconfiguration TimeIdle Time Line ProtocolAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Cable Type Impedance AT 5MHZ Functional DescriptionAttenuation NominalRead Register Summary Write Tentative ID Register Internal RegistersInterrupt Mask Register IMR Data RegisterStatus Register Diagnostic Status RegisterCommand Register Next ID RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Software Interface Sequential Access MemoryAccess Speed Internal RAMTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator Operational Description Maximum Guaranteed RatingsDC Electrical Characteristics Parameter Symbol MIN TYP MAX Unit CommentXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp