SMSC COM20020 manual Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle

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AD0-AD2, D3-D7

nCS

ALE

nWR

VALID

t1 t2, t4

t3

t5

VALID DATA

t7

t6 Note 2

t8**

t8

	Parameter	min	max	units

t1	Address Setup to ALE Low	30		nS
t2	Address Hold from ALE Low	10		nS
t3	nCS Setup to ALE Low	10		nS
t4	nCS Hold from ALE Low	20		nS
t5	ALE Low to nWR Low	15		nS
t6	Valid Data Setup to nWR High	30		nS
t7	Data Hold from nWR High	10		nS
t8	Cycle Time (nWR Low to Next Time Low)**	4T*		nS

*T is the Arbitration Clock Period.

T is identical to XTAL1 if SLOW ARB = 0, T is twice XTAL1 period if SLOW ARB = 1

Note 1: The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020 cycles.

**Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a minimum of 4T from the trailing edge of nWR to the leading edge of the next nWR.

FIGURE 11A - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsTransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Protocol Description Network ReconfigurationNetwork Protocol Data RatesBroadcast Messages Extended Timeout FunctionResponse Time Idle Time Reconfiguration TimeLine Protocol Invitations To TransmitAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Attenuation Functional DescriptionNominal Cable Type Impedance AT 5MHZRead Register Summary Write Interrupt Mask Register IMR Internal RegistersData Register Tentative ID RegisterCommand Register Diagnostic Status RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Access Speed Sequential Access MemoryInternal RAM Software InterfaceTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator DC Electrical Characteristics Maximum Guaranteed RatingsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp