SMSC COM20020 manual NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle

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A0-A2

t1

VALID

t2

nCS

t4

DIR

t3

t7

t5

t6

nDS

t8

t9

D0-D7

VALID DATA

Parameter

min

max

units

t1

Address Setup to nDS Active

15

nS

t2

Address Hold from nDS Inactive

10

nS

t3

nCS Setup to DS Active

5**

nS

t4

nCS Hold from DS Inactive

0

nS

t5

DIR Setup to nDS Active

10

nS

t6

Cycle Time (nDS Low to Next Time Low)

4T*

nS

t7

DIR Hold from nDS Active

10

nS

t8

nDS Low to Valid Data

40

nS

t9

nDS High to Data High Impedence

0

20

nS

*T is the Arbitration Clock Period.

T is identical to XTAL1 if SLOW ARB = 0, T is twice XTAL1 period if SLOW ARB = 1

**nCS may become active after control becomes active, but the access time will now be 45nS measured from the leading edge of nCS.

Note 1: The Microcontroller typically accesses the COM20020 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020 cycles.

FIGURE 12A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Data Rates Network ReconfigurationProtocol Description Network ProtocolExtended Timeout Function Broadcast MessagesResponse Time Invitations To Transmit Reconfiguration TimeIdle Time Line ProtocolData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Cable Type Impedance AT 5MHZ Functional DescriptionAttenuation NominalRead Register Summary Write Tentative ID Register Internal RegistersInterrupt Mask Register IMR Data RegisterStatus Register Diagnostic Status RegisterCommand Register Next ID RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Software Interface Sequential Access MemoryAccess Speed Internal RAMTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator Operational Description Maximum Guaranteed RatingsDC Electrical Characteristics Parameter Symbol MIN TYP MAX Unit CommentXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp