SMSC COM20020 manual Date, SECTION/FIGURE/ENTRY Correction Revised

Page 59

COM20020 ERRATA SHEET

			DATE
PAGE	SECTION/FIGURE/ENTRY	CORRECTION	REVISED
PAGE	SECTION/FIGURE/ENTRY	CORRECTION

5	Pin No. 18/DESCRIPTION	See Italicized Text	5/29/96

8	Network Protocol	See Italicized Text	5/29/96

9	Network Reconfiguration	See Italicized Text	5/29/96

9	Extended Timeout Function	See Italicized Text	5/29/96

10	Line Protocol	See Italicized Text	5/29/96

12	Microcontroller Interface	See Italicized Text	5/29/96

15	Backplane Configuration	See Italicized Text	5/29/96

17	Programmable TXEN Polarity	See Italicized Text	5/29/96

22	Data Register	See Italicized Text	5/29/96

23	Status Register	See Italicized Text	5/29/96

23	Address Pointer Registers	See Italicized Text	5/29/96

24	Configuration Register	See Italicized Text	5/29/96

29	Table 9	Bits 4,3 - See Italicized Text	5/29/96

30	Table 10	Bit 5 and Bits 3,2,1 - See Italicized	5/29/96
		Text

35	Transmit Sequence	See Italicized Text	5/29/96

40	Bus Determination	See Italicized Text	5/29/96

42	Abnormal Results	See Italicized Text	5/29/96

59

Image 59

Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsMiscellaneous DIP PIN Plcc PIN Name Symbol DescriptionTransmission Media Interface Instead, it must be connected to XTAL1 with COM20020 Operation Data Rates Network ReconfigurationProtocol Description Network ProtocolResponse Time Extended Timeout FunctionBroadcast Messages Invitations To Transmit Reconfiguration TimeIdle Time Line ProtocolNegative Acknowledgements Data PacketsAcknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Cable Type Impedance AT 5MHZ Functional DescriptionAttenuation NominalRead Register Summary Write Tentative ID Register Internal RegistersInterrupt Mask Register IMR Data RegisterStatus Register Diagnostic Status RegisterCommand Register Next ID RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Software Interface Sequential Access MemoryAccess Speed Internal RAMTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator Operational Description Maximum Guaranteed RatingsDC Electrical Characteristics Parameter Symbol MIN TYP MAX Unit CommentXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp