SMSC COM20020 manual CKP3 CKP2 CKP1

Page 30

Table 10 - Setup Register

BIT

BIT NAME

SYMBOL

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

7

Pulse1 Mode

P1MODE

This bit

determines the type of PULSE1 output driver used in

 

 

 

 

Backplane Mode. When high, a push/pull output is used. When

 

 

 

 

low, an open drain output is used. The default is open drain.

 

 

 

 

 

 

6

Four NACKS

FOUR

This bit, when set, will cause the EXNACK bit in the Diagnostic

 

 

 

NACKS

Status Register to set after four NACKs to Free Buffer Enquiry are

 

 

 

 

detected by the COM20020. This bit, when reset, will set the

 

 

 

 

EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default

 

 

 

 

is 128.

 

 

 

 

 

 

 

 

 

 

 

5

ET3

ET3

This bit,

when set, scales down protocol timeout values of

 

 

 

 

Response Time and Idle Time but not Reconfiguration Time to

 

 

 

 

optimize network performance in short topologies. Provides a

 

 

 

 

scaling factor of ÷ 3. Defaults to a zero. Must be reset to be

 

 

 

 

ARCNET compliant.

 

 

 

 

 

 

 

 

4

Receive All

RCVALL

This bit, when set, allows the COM20020 to receive all valid data

 

 

 

 

packets on the network, regardless of their destination ID. This

 

 

 

 

mode can be used to implement a network monitor with the

 

 

 

 

transmitter on- or off-line. Note that ACKs are only sent for packets

 

 

 

 

received with a destination ID equal to the COM20020's

 

 

 

 

programmed node ID. This feature can be used to put the

 

 

 

 

COM20020 in a 'listen-only' mode, where the transmitter is disabled

 

 

 

 

and the COM20020 is not passing tokens. Defaults low.

 

 

 

 

 

 

3,2,1

Clock Prescaler Bits

CKP3,2,1

These bits are used to determine the data rate of the COM20020.

 

 

3,2,1

 

The following table is for a 20MHz crystal:

 

 

 

 

 

CKP3

CKP2

CKP1

DIVISOR

SPEED

 

 

 

 

0

0

0

8

2.5Mbs

 

 

 

 

0

0

1

16

1.25Mbs

 

 

 

 

0

1

0

32

625Kbs

 

 

 

 

0

1

1

64

312.5Kbs

 

 

 

 

1

0

0

128

156.25Kbs

 

 

 

 

1

0

1

256

Reserved

 

 

 

 

1

1

0

 

Reserved

 

 

 

 

1

1

1

 

Reserved

 

 

 

 

NOTE: The lowest data rate achievable by the COM20020 is

 

 

 

 

156.25Kbs. A divide by 256 is provided for those systems that use

 

 

 

 

faster clock speeds. Defaults to 000 or 2.5Mbs.

 

 

 

 

 

 

 

0

Slow Arbitration Select

SLW-ARB

This bit, when set, will divide the arbitration clock by 2. Memory

 

 

 

 

cycle times will increase when slow arbitration is selected.

 

 

 

 

NOTE: For clock speeds greater than 20MHz, SLOWARB must be

 

 

 

 

set. Defaults to low.

 

 

 

 

 

 

 

 

 

 

 

 

30

Page 29 Page 31
Image 30
Page 29 Page 31
Contents Features General DescriptionTable of Contents PIN Configuration Description of PIN Functions A1,A2/ALEDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Network Protocol Network ReconfigurationProtocol Description Data RatesExtended Timeout Function Broadcast MessagesResponse Time Line Protocol Reconfiguration TimeIdle Time Invitations To TransmitData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Backplane Configuration Traditional Hybrid InterfaceCOM20020 Network Using RS-485 Differential Transceivers Differential Driver Configuration Programmable Txen PolarityInternal Block Diagram Nominal Functional DescriptionAttenuation Cable Type Impedance AT 5MHZRead Register Summary Write Data Register Internal RegistersInterrupt Mask Register IMR Tentative ID RegisterNext ID Register Diagnostic Status RegisterCommand Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description BIT BIT Name Symbol Description DupidData Command Description Address Pointer High Register Address Pointer Low RegisterConfiguration Register ResetCKP3 CKP2 CKP1 Sequential Access Operation Internal RAM Sequential Access MemoryAccess Speed Software InterfaceSelecting RAM Page Size Transmit SequenceRAM Buffer Packet Configuration Page Receive Sequence Command Chaining Transmit Command ChainingReceive Command Chaining Reset Details Internal Reset LogicImproved Diagnostics Initialization SequenceNormal Results Abnormal ResultsOscillator Parameter Symbol MIN TYP MAX Unit Comment Maximum Guaranteed RatingsDC Electrical Characteristics Operational DescriptionXTAL1, XTAL2 Input Capacitance Timing Diagrams Multiplexed BUS, 68XX-LIKE Control Signals Read CycleMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle Normal Mode Transmit or Receive Timing These signals are to and from the hybridNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions Date SECTION/FIGURE/ENTRY Correction RevisedStandard Microsystems Corp
Top Page Image Contents