SMSC COM20020 manual Input Capacitance

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CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V)

Output and I/O pins capacitive load specified as follows:

PARAMETER	SYMBOL	MIN	TYP	MAX	UNIT	COMMENT

Input Capacitance	CIN			5.0	pF

Output Capacitance 1	COUT1			45	pF	Maximum
(All outputs except						Capacitive Load
nPULSE1 in BackPlane						which can be
Mode)						supported by each
Output Capacitance 2	COUT2			400	pF	output.
(nPULSE1, in
BackPlane
Mode Only - Open
Drain)

AC Measurements are taken at the following points:

Inputs:Outputs:

t

	t
2.4V	2.0V
2.4V
1.4V	50%
	50%

0.4V	0.8V

2.4V	t
	t				2.0V
					2.0V
1.4V


0.4V	50%
0.4V					0.8V

t

Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0".

Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsDIP PIN Plcc PIN Name Symbol Description Transmission Media InterfaceMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Protocol Description Network ReconfigurationNetwork Protocol Data RatesExtended Timeout Function Broadcast MessagesResponse Time Idle Time Reconfiguration TimeLine Protocol Invitations To TransmitData Packets AcknowledgementsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Attenuation Functional DescriptionNominal Cable Type Impedance AT 5MHZRead Register Summary Write Interrupt Mask Register IMR Internal RegistersData Register Tentative ID RegisterCommand Register Diagnostic Status RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Access Speed Sequential Access MemoryInternal RAM Software InterfaceTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal Results Oscillator DC Electrical Characteristics Maximum Guaranteed RatingsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp