SMSC COM20020 manual BIT BIT Name Symbol Description

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Table 4 - Status Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

 

 

 

 

7

Receiver

RI

This bit, if high, indicates that the receiver is not enabled because either

 

Inhibited

 

an "Enable Receive to Page fnn" command was never issued, or a

 

 

 

packet has been deposited into the RAM buffer page fnn as specified by

 

 

 

the last "Enable Receive to Page fnn" command. No messages will be

 

 

 

received until this command is issued, and once the message has been

 

 

 

received, the RI bit is set, thereby inhibiting the receiver. The RI bit is

 

 

 

cleared by issuing an "Enable Receive to Page fnn" command. This bit,

 

 

 

when set, will cause an interrupt if the corresponding bit of the Interrupt

 

 

 

Mask Register (IMR) is also set. When this bit is set and another

 

 

 

station attempts to send a packet to this station, this station will send a

 

 

 

NAK.

 

 

 

 

6,5

(Reserved)

 

These bits are undefined.

 

 

 

 

4

Power On Reset

POR

This bit, if high, indicates that the COM20020 has been reset by either a

 

 

 

software reset, a hardware reset, or writing 00H to the Node ID

 

 

 

Register. The POR bit is cleared by the "Clear Flags" command.

 

 

 

 

3

Test

TEST

This bit is intended for test and diagnostic purposes. It is a logic "0"

 

 

 

under normal operating conditions.

 

 

 

 

2

Reconfiguration

RECON

This bit, if high, indicates that the Line Idle Timer has timed out because

 

 

 

the RXIN pin was idle for 82μS. The RECON bit is cleared during a

 

 

 

"Clear Flags" command. This bit, when set, will cause an interrupt if the

 

 

 

corresponding bit in the IMR is also set. The interrupt service routine

 

 

 

should consist of examining the MYRECON bit of the Diagnostic Status

 

 

 

Register to determine whether there are consecutive reconfigurations

 

 

 

caused by this node.

 

 

 

 

1

Transmitter

TMA

This bit, if high, indicates that the packet transmitted as a result of an

 

Message

 

"Enable Transmit from Page fnn" command has been acknowledged.

 

Acknowledged

 

This bit should only be considered valid after the TA bit (bit 0) is set.

 

 

 

Broadcast messages are never acknowledged. The TMA bit is cleared

 

 

 

by issuing the "Enable Transmit from Page fnn" command.

 

 

 

 

0

Transmitter

TA

This bit, if high, indicates that the transmitter is available for

 

Available

 

transmitting. This bit is set when the last byte of scheduled packet has

 

 

 

been transmitted out, or upon execution of a "Disable Transmitter"

 

 

 

command. The TA bit is cleared by issuing the "Enable Transmit from

 

 

 

Page fnn" command after the node next receives the token. This bit,

 

 

 

when set, will cause an interrupt if the corresponding bit in the IMR is

 

 

 

also set.

 

 

 

 

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Contents General Description FeaturesTable of Contents PIN Configuration A1,A2/ALE Description of PIN FunctionsTransmission Media Interface DIP PIN Plcc PIN Name Symbol DescriptionMiscellaneous Instead, it must be connected to XTAL1 with COM20020 Operation Protocol Description Network ReconfigurationNetwork Protocol Data RatesBroadcast Messages Extended Timeout FunctionResponse Time Idle Time Reconfiguration TimeLine Protocol Invitations To TransmitAcknowledgements Data PacketsNegative Acknowledgements System Description MULTIPLEXED, 8051-LIKE BUS Interface with RS-485 Interface Figure C Traditional Hybrid Interface Backplane ConfigurationCOM20020 Network Using RS-485 Differential Transceivers Programmable Txen Polarity Differential Driver ConfigurationInternal Block Diagram Attenuation Functional DescriptionNominal Cable Type Impedance AT 5MHZRead Register Summary Write Interrupt Mask Register IMR Internal Registers Data Register Tentative ID RegisterCommand Register Diagnostic Status RegisterNext ID Register Status RegisterConfiguration Register Setup Register BIT BIT Name Symbol Description Dupid BIT BIT Name Symbol DescriptionData Command Description Address Pointer Low Register Address Pointer High RegisterReset Configuration RegisterCKP3 CKP2 CKP1 Sequential Access Operation Access Speed Sequential Access MemoryInternal RAM Software InterfaceTransmit Sequence Selecting RAM Page SizeRAM Buffer Packet Configuration Page Receive Sequence Transmit Command Chaining Command ChainingReceive Command Chaining Internal Reset Logic Reset DetailsInitialization Sequence Improved DiagnosticsAbnormal Results Normal ResultsOscillator DC Electrical Characteristics Maximum Guaranteed RatingsParameter Symbol MIN TYP MAX Unit Comment Operational DescriptionXTAL1, XTAL2 Input Capacitance Multiplexed BUS, 68XX-LIKE Control Signals Read Cycle Timing DiagramsMultiplexed BUS, 80XX-LIKE Control Signals Read Cycle Multiplexed BUS, 68XX-LIKE Control Signals Write Cycle Multiplexed BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Read Cycle NON-MULTIPLEXED BUS, 80XX-LIKE Control Signals Write Cycle NON-MULTIPLEXED BUS, 68XX-LIKE Control Signals Write Cycle These signals are to and from the hybrid Normal Mode Transmit or Receive TimingNTXEN NPULSE1 TTL Input Timing on XTAL1 PIN 28-PIN Plcc Package Dimensions 24-PIN DIP Package Dimensions SECTION/FIGURE/ENTRY Correction Revised DateStandard Microsystems Corp
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